* add axi parameters to cfg
* Move axi_intf.sv from core to corev_apu
* Move ariane_axi_pkg.sv from core to corev_apu
* Merge axi and l15 into noc
* Fixes to build and run openpiton
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jonathan Balkind <jbalkind@ucsb.edu>
Parametrise the AXI interface of CVA6. With this PR, both cache subsystems support variable AXI address widths. The write-through cache furthermore supports variable AXI data widths. Moreover, this PR includes a modular AXI testbench for the WT cache to test the introduced changes. The following configurations of the WT cache have been verified:
XLEN Cacheline Width AXI data width AXI address width
64 128 64 64
64 128 128 52
64 512 128 64
32 512 256 48
32 64 32 48
This PR does the following
1. Bump the filelist for OpenPiton for new directory layout
2. Remove AXI Interface for OpenPiton in the top level
3. Fix several issues in MMU discovered during address translation last year, the changes in core/mmu_sv39/mmu.sv are a joint effort between Jbalkind minho-pulp zarubaf niwis acostillado tianrui-wei
4. disable bitmanip by default
5. separate an ariane config package for openpiton synthesis. Some of the previous changes makes ariane too big for openpiton, so we need to revert these changes
6. Don't increase number of writeback ports (NR_WB_PORTS) when cvxif is not enabled
