9 commits

Author	SHA1	Message	Date
Jean-Roch Coulon	2ec24264e4	Add vcs-uvm-gate ISS target	2024-10-08 21:14:33 +02:00
Zbigniew Chamski	48ef515ba0	[Spike Yaml] Integrate Spike Yaml support. (#2304)	2024-07-11 08:37:37 +02:00
isabelle schmid	c36837142f	Add xrun-testharness	2024-06-12 11:01:15 +02:00
isabelle schmid	27836559ae	Add xrun-uvm options	2024-06-12 11:01:15 +02:00
Guillaume Chauvon	a5152b03a5	Add support for cv32a65x dedicated synthesis (#2178)	2024-06-04 10:58:09 +02:00
valentinThomazic	3dc1f23a9d	Support Spike Parameters in cva6.py and bump core-v-verif (#1976)	2024-04-02 10:26:25 +02:00
MarioOpenHWGroup	62bdf11594	Bump core-v-verif d94f0de and fix questa simulator (#1915)	2024-03-21 19:02:41 +01:00
MarioOpenHWGroup	8b6e8295f8	Add priv level to cva6.py and fix smoke-tests (#1768)	2024-01-17 23:14:19 +01:00
Côme Allart	736be43a73	move files to a verif directory	2023-09-07 09:50:50 +02:00

Renamed from cva6/sim/cva6.yaml (Browse further)