Jean-Roch Coulon
e7f423404f
Set clock period at 20ns and fix vcs-uvm simulation time
2024-10-08 21:14:33 +02:00
Jean-Roch Coulon
2ec24264e4
Add vcs-uvm-gate ISS target
2024-10-08 21:14:33 +02:00
Cesar Fuguet
8f06d41850
Update RESOURCES.md ( #2530 )
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Add an item pointing to the HPDcache in the related building blocks section
Co-authored-by: Jérôme Quévremont <jerome.quevremont@thalesgroup.com>
2024-10-04 18:45:34 +02:00
JeanRochCoulon
08c81658ec
Display report at the end of dhrystone and coremark executions ( #2529 )
2024-10-04 17:52:06 +02:00
Jérôme Quévremont
4a642d35d9
Resources and ecosystem ( #2514 )
2024-10-04 15:21:17 +02:00
JeanRochCoulon
51653c6377
Revert "[PMP] Extracted PMP ( #2476 )" ( #2524 )
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This reverts commit 969c1518f2
2024-10-04 07:39:35 +02:00
CoralieAllioux
969c1518f2
[PMP] Extracted PMP ( #2476 )
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* Remove misaligned_ex computation: get it from outside
* Remove data and instr pmps, get match_execution from outside
* Get data and instr allow from outside
* Simplify fetch_instruction exception when instr not allow by pmp
* Simplify exception when data not allow by pmp, getting it from outside
* Apply verible format
* First public version of extracted pmp
* Integrate PMP fully outside MMU
* fix translation_valid and dtlb_ppn when no mmu
* Add pmp_data_if in needed file lists
* Fix exception tval when translation is enabled
* integrate no_locked assertions for pmp: now in blocking assignments to avoid raise condition in simulation
* Fix mixed assignment for no_locked_if
* Remove assertion no_locked from pmp: need clk and reset
* Apply verible format
---------
Co-authored-by: Olivier Betschi <olivier.betschi@fr.bosch.com>
2024-10-03 08:21:56 +00:00
Zbigniew Chamski
44072bfd83
[pmpcfg detailed spec] Add proposed CSR spec output. ( #2522 )
2024-10-02 23:32:12 +02:00
Andrea
ff01467041
Fixed btb for FPGA targets ( #2521 )
2024-10-02 23:31:40 +02:00
JeanRochCoulon
c6ae849f7a
put dhrystone in smoke job group and coremark in regress job group ( #2520 )
2024-10-01 08:56:42 +02:00
jzthales
6ccd8d8bfa
Refactor forwarding in issue_stage module ( #2519 )
2024-10-01 06:13:30 +02:00
JeanRochCoulon
56532c6963
Simplify CI ( #2517 )
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Modify CI to always check with Tandem and promote UVM TB use
2024-09-27 10:01:46 +02:00
Nils Wistoff
860f47fed7
ci: Update phiwag/edatools gpg key ( #2515 )
2024-09-26 22:46:14 +02:00
dependabot[bot]
967fc5d021
Bump verif/core-v-verif from c3d0c72 to 4e17969 ( #2512 )
2024-09-24 23:24:11 +02:00
AEzzejjari
923d9c2e8f
Drive the AXI interface slave signals with 'Z in the active mode ( #2511 )
2024-09-24 18:24:52 +02:00
Riccardo Tedeschi
164d7c7fc9
Add AW lock register to handle W FIFO push signal ( #2461 )
2024-09-24 08:42:16 +02:00
Zbigniew Chamski
bc7eeb7b01
[interrupt verification] Add .uvmif support to global verif linker script ( #2507 )
2024-09-23 17:51:14 +02:00
Zbigniew Chamski
f974e105bf
Add a basic mechanism for interrupt acknowledge. ( #2502 )
2024-09-19 18:31:42 +02:00
André Sintzoff
8070febca0
spyglass: remove W528 warnings in decoder.sv ( #2503 )
2024-09-19 15:45:36 +02:00
Jalali
6a4af755aa
UVM environment: mcountinhibit doesn't raise an exception ( #2494 )
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fix in UVM environment after fixed RTL bug on mcountinhibit
(commit faf4536
2024-09-06 14:31:12 +02:00
MarioOpenHWGroup
e9382ba3ac
Bump verif/core-v-verif csr-injection ( #2491 )
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* Bump cvv/csr-injection
* Bump core-v-verif
* [ci] try to fix the CI
* [ci] fix lint
* [ci] Fix stages
* [ci] Deprecated set-output
2024-09-04 17:39:34 +02:00
André Sintzoff
6561f2c641
report_benchmark.py: fix Dhrystone cycles after PR #2484 ( #2488 )
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after commit 111df66
2024-09-02 16:39:12 +02:00
dependabot[bot]
ea3a55450b
Bump core/cache_subsystem/hpdcache from 25ffa34 to b4519e7 ( #2466 )
2024-08-31 08:51:52 +02:00
valentinThomazic
9362816e1c
fix simulation errors not detected on ci w/ tandem ( #2486 )
2024-08-30 22:23:03 +02:00
AEzzejjari
d577aaf850
Fix vcs-uvm simulation flow ( #2485 )
2024-08-30 17:57:35 +02:00
JeanRochCoulon
8ef28596d5
Code clean-up of the number of register address bits ( #2483 )
2024-08-30 17:22:53 +02:00
JeanRochCoulon
111df66d27
fix hwconfig setup in cva6.py ( #2484 )
2024-08-30 17:09:23 +02:00
valentinThomazic
a66efad475
fix jal riscv-arch-test ( #2479 )
2024-08-30 07:13:04 +02:00
AEzzejjari
668829de6e
Set the environment configuration only from env_cfg constraints. ( #2408 )
2024-08-29 18:00:32 +02:00
MarioOpenHWGroup
776e0137b6
[RVFI] Connect RVFI.intr to enable interrupts on TANDEM ( #2475 )
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* [RVFI] Connect rvfi
* Lower verbosity to uvme_axi_covg
* Add unified_traps as a param for yaml
* Apply suggestions from code review
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
---------
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
2024-08-29 11:33:42 +02:00
MarioOpenHWGroup
6249bd1929
[TANDEM] CSR Params Refactor + CSR API ( #2407 )
2024-08-28 12:25:41 +02:00
valentinThomazic
004f819c14
Tandem for 65x ( #2473 )
2024-08-28 11:19:44 +02:00
Côme
0d2097be0c
Fix minstret ( #2471 )
2024-08-28 10:54:52 +02:00
JeanRochCoulon
faf4536b37
fix #2464 : exception is not generated when INHIBIT CSR is accessed ( #2468 )
2024-08-27 10:38:48 +02:00
valentinThomazic
53b51ac5a7
do not use tandem on test suites in ci ( #2463 )
2024-08-26 23:56:51 +02:00
Côme
339d3dd851
Increase code coverage on second ALU by removing branch logic ( #2362 )
2024-08-26 17:32:24 +02:00
Côme
064cec2066
fix missing ZCMP condition in commit stage to increasse Code Coverage ( #2459 )
2024-08-24 11:48:36 +02:00
Côme
4c36aafaf0
fix CI ( #2460 )
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* fix .gitlab-ci.yml
* Update report_tandem.py
2024-08-23 11:34:17 -04:00
EasyIP2023
37b58243fa
docs: expand wy-nav-content width to edge of screen ( #2452 )
2024-08-22 18:10:19 +02:00
valentinThomazic
28affa2346
[CI] use spike tandem on smoke-tests ( #2438 )
2024-08-22 17:04:48 +02:00
Côme
76e5b40961
fix single-step which was x in cv32a65x config and fix mcycle for double commit ( #2369 )
2024-08-22 12:03:20 +02:00
dependabot[bot]
12f41b52ac
Bump verif/core-v-verif from e06bd57 to 628ba12 ( #2456 )
2024-08-20 08:37:35 +02:00
André Sintzoff
051ba348f9
spyglass: remove WRN_1024 warnings ( #2448 )
2024-08-19 15:44:30 +02:00
Zbigniew Chamski
89eb77a249
[Spike tandem] Fix Yaml config files for CV32A65X. Fix Questa tandem. Add workaround for AXI end-of-test asserts. ( #2436 )
2024-08-19 11:09:32 +02:00
André Sintzoff
834e3e74d5
spyglass: ignore some multiple assignment W415a warnings ( #2446 )
2024-08-14 14:17:38 +02:00
JeanRochCoulon
d2889fa174
Display number of cycles at test termination ( #2443 )
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Reported by RVFI_tracer module
2024-08-13 17:12:13 +02:00
André Sintzoff
e5618977d1
spyglass: move assignments in if clause as only used there ( #2444 )
2024-08-13 17:11:10 +02:00
Guillaume Chauvon
4f45b575aa
Add ariane_peripherals and testharness to fpga_filter ( #2445 )
2024-08-13 16:18:11 +02:00
Jalali
9b576c1200
Configure uvm scoreboard to fix 64 issue ( #2440 )
2024-08-13 09:16:54 +02:00
André Sintzoff
af4e3744d4
spyglass: remove useless assignments ( #2439 )
2024-08-12 15:06:39 +02:00
