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Author SHA1 Message Date
Florian Zaruba
259e089ae3 🚧 Parameterize register file (FPU preparation) 2018-04-18 14:53:47 +02:00
Stefan Mach
4e8aa09384 🚧 Add FP operations to load/store unit 2018-04-18 14:53:47 +02:00
Stefan Mach
4d5fa5adbb 🚧 Add FP operations to compressed decoder 2018-04-18 14:53:47 +02:00
Stefan Mach
8cb26a39e2 🚧 Add FP extensions to decoder 2018-04-18 14:53:46 +02:00
Stefan Mach
d2460f3048 🐛 Fix FP CSR writes do not cause flush 2018-04-18 14:53:46 +02:00
Stefan Mach
a98d907b35 ♻️ Update frontend for refactored opcodes 2018-04-18 14:53:46 +02:00
Stefan Mach
0cd0b1212e ♻️ Refactor opcode names and decoders 
Refactoring opcode names to be as specified in the RISC-V spec.
Also added all opcodes defined in the spec for (potential) future use.
 2018-04-18 14:53:46 +02:00
Stefan Mach
280abe8853 🚧 Add Floating-Point CSR 
Add FP CSRs `fcsr`, `fflags` and `frm` to the core.
 2018-04-18 14:53:41 +02:00
Florian Zaruba
0683cedce3
Adapt src_files.yml to reflect src file changes 2018-03-21 09:45:41 +01:00
Florian Zaruba
59cc64e6f6
Set sane values for BHT, BTB and RAS 2018-03-19 14:33:22 +01:00
Fabian Schuiki
645dcfcb6e Remove regfile_ff from bender file 
Both `ariane_regfile.sv` and `ariane_regfile_ff.sv` define a module
`ariane_regfile.sv`. Drop the latter.
 2018-03-16 16:37:17 +01:00
Florian Zaruba
e662606cdb
Add new regfiles to Bender 2018-03-16 13:29:46 +01:00
Florian Zaruba
a712ad8afc
Remove potential collisions on regfile 2018-03-16 13:18:15 +01:00
Florian Zaruba
594d4687e9
Merge branch 'new-frontend' into ariane_next 2018-03-14 14:35:49 +01:00
Florian Zaruba
d90a9b00a0
🐛 Fix encoding issue (undetected illegal instr) 2018-03-14 14:10:54 +01:00
Florian Zaruba
96eb8cdf26
Merge pull request #22 from raulbehl/master 
README update for (fix #21)
 2018-03-14 12:50:30 +01:00
Florian Zaruba
e06811993c
Update .travis.yml 2018-03-14 11:33:15 +01:00
Florian Zaruba
0ccf5d4572
Fix #23 2018-03-14 10:48:51 +01:00
Florian Zaruba
9ed38d1a83
Benderize ariane src_files 2018-03-14 10:44:22 +01:00
Florian Zaruba
9566d03b54
Update .travis.yml 2018-03-14 10:40:19 +01:00
Florian Zaruba
8ade9c2384
Update riscv-gcc 2018-03-14 10:01:12 +01:00
Florian Zaruba
38b0ff8866
Pump riscv-toolchain version for CI build 2018-03-14 09:51:45 +01:00
Rahul Behl
7155c8b33e
README update for #21 
- Added a new section in README about compiling custom C-code
 2018-03-14 11:57:13 +05:30
Florian Zaruba
971c3ce704
Merge pull request #17 from raulbehl/master 
Fixes for #16
 2018-03-08 08:56:02 +01:00
raulbehl
82a9a345e5 🎨 Fixes for #16 
- Updated simc target to automatically run the test by adding
    run -a in the do command
 2018-03-08 00:33:13 +05:30
Florian Zaruba
c74bb21d21
Merge pull request #15 from raulbehl/alu_brn_resolve 
✂️ Changes for #1
 2018-03-06 17:48:43 +01:00
Rahul Behl
50506f8d34
Update alu.sv based on review comments 
Updated the if condition to use "||" instead of "|" operator
 2018-03-06 22:17:02 +05:30
Florian Zaruba
62fffe6a9a
Add correct dependencies 2018-03-06 17:20:47 +01:00
raulbehl
8f2c2a0499 ✂️ Changes for #1 
- Moved the branch resolve engine to ALU
  - Updated conditions in the ALU code to account for different
    type of branches as well
  - Update the port definitions wherever required
 2018-03-05 19:14:22 +05:30
Florian Zaruba
18db8ee9a7
🐛 Close #13 2018-03-05 13:59:23 +01:00
Florian Zaruba
1dba4d6916
Merge pull request #14 from raulbehl/master 
Fix for #10
 2018-03-05 13:40:59 +01:00
Rahul Behl
381b90476f
Update Makefile 
- Added back the elfdpi.h creation as it is required by build-dpi target
 2018-03-04 19:35:53 +05:30
raulbehl
11afcad9c2 Fix for #10 
- Added build-dpi target in Make to compile DPI C-code using gcc
  - Updated the vsim commands in the Makefile to include the newly
    generated DPI library
  - Updated the vsim command with the "-64" switch as we are always
    using this switch with vlog
 2018-03-04 17:09:45 +05:30
Florian Zaruba
038357ae3d
📝 Add documentation on generating hex file 2018-03-02 11:25:39 +01:00
Florian Zaruba
5d83f69e80
🐛 Resolve issue #12 2018-03-02 11:16:57 +01:00
Florian Zaruba
cfd392415b
Remove unintentional reduction operator 2018-03-02 11:09:02 +01:00
Florian Zaruba
3c6e29f23b
Merge pull request #9 from olofk/fusesoc 
Add FuseSoC support for building verilator model
 2018-02-28 10:47:45 +01:00
Olof Kindgren
dd0a00d3b4 Add FuseSoC support for building verilator model 2018-02-27 22:34:35 +01:00
Florian Zaruba
f4ac81e225
Improve synthesis results 2018-02-25 11:21:15 +01:00
Florian Zaruba
997691748e Merge branch 'master' of github.com:pulp-platform/ariane into new-frontend 2018-02-22 12:32:14 +01:00
Florian Zaruba
aba53f37e0
Fix synthesis problems in miss handler 2018-02-22 00:28:25 +01:00
Florian Zaruba
8a326f76bb
📝 Correct from checking out to cloning 2018-02-19 20:33:02 +01:00
Florian Zaruba
d58ab98bf8
📝 Explicitly mention riscv-fesvr in README 2018-02-16 14:04:36 +01:00
Florian Zaruba
6c66ea19ae VM based RISC-V tests are passing 2018-02-16 12:39:44 +01:00
Florian Zaruba
f2d45c007b Simplfy instruction address translation 2018-02-16 11:07:30 +01:00
Florian Zaruba
96a8e3165e Improve IPC, remove tag signal from icache 2018-02-16 10:15:11 +01:00
Florian Zaruba
a4dc0bba59 Remove latch 2018-02-15 18:38:57 +01:00
Florian Zaruba
ec5ef97d55 Implement RVC without RVI perf impact 2018-02-15 18:23:00 +01:00
Florian Zaruba
ad92456cb3 Remove branch-resolving logic in issue stage 2018-02-15 11:13:58 +01:00
Florian Zaruba
c57ce142e7 Update BHT and BTB separately 
Dhrystone > 1.7 DMIPS
 2018-02-14 17:31:02 +01:00