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9 commits

Author SHA1 Message Date
André Sintzoff
5c3007db53
docs: add CV32A60X configuration in RISC-V ISA manual (#2806)
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* docs: spec_builder.py: add missing extensions
* docs: fix unpriv manual (opcode map, Zcmop)
- in opcode map, write not used when corresponding extension is disabled
- use correct condition for Zcmop extension
* docs: remove PMP chapter when no PMP
* docs: add tailored RISC-V ISA manual for CV32A60X configuration
2025-03-04 13:47:22 +01:00
André Sintzoff
8e5872c03b
update riscv-isa-manual to riscv-isa-release-4f277ff-2025-01-17 (#2717)
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Since last riscv-isa-manual update (CVA6 commit 67a6ae966):
	- minor documentation changes
	- new unsupported Zsmctr extension
	- add missing asciidoctor-lists gem in dependencies/Gemfile

Gemfile update is needed for ReadTheDocs

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-01-21 09:56:51 +01:00
slgth
ab2283c075
doc: keep documentation in sync with the code (#2558)
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Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters).
As of now, they are committed to the repository and can be out of sync with the code.

This PR removes them from the repository and freshly generates them from the code when building HTML files.

This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
2024-10-25 12:27:09 +02:00
slgth
e9648eaf8c
Design documentation: AsciiDoc conversion (#2399) 2024-07-25 17:18:27 +02:00
Côme
0cbd894a7a
update port and config docs (#2363) 2024-07-12 17:00:36 +02:00
slgth
b1850a8cb7
docs: fix spec_builder.py (#2249) 2024-06-12 20:07:22 +02:00
JeanRochCoulon
57f062bd85
Add Caches submodule description in Design Doc (#1923) 2024-03-12 17:40:05 +01:00
JeanRochCoulon
f332688fc0
Complete Design Document (#1865) 2024-02-23 23:09:11 +01:00
JeanRochCoulon
b4c287a18e
Design Document, add ID_STAGE description (#1832) 2024-02-16 16:17:46 +01:00