11 commits

Author	SHA1	Message	Date
slgth	6a649d6515	docs: more fixes (#2412)	2024-07-26 23:49:41 +02:00
Zbigniew Chamski	96b0508525	[riscv-config] Update PMP definitions in cv32q65x spec (#2401)	2024-07-25 22:06:51 +02:00
AbdessamiiOukalrazqou	b438a8ba8e	[gen_from_riscv_config] Improve the tool to support debug spec (#2398)	2024-07-25 20:07:45 +02:00
slgth	e9648eaf8c	Design documentation: AsciiDoc conversion (#2399)	2024-07-25 17:18:27 +02:00
AbdessamiiOukalrazqou	5f8605838e	[gen_from_riscv_config] fix access issues for PMP registers, improve Factorization algorithm , improve csr_updater.yaml, add spike support (#2372)	2024-07-21 22:39:50 +02:00
AbdessamiiOukalrazqou	ee0847e30a	[gen_from_riscv_config] add custom-gen.yaml support / fix hyperlinks in csr design doc / improve readme/fix csr_updater.yaml (#2286)	2024-06-21 17:19:42 +02:00
Zbigniew Chamski	17ea49439f	[riscv-config] Update riscv-config tool, CV32A65X specs and the rendering of CSRs. (#2270)	2024-06-19 12:08:15 +02:00
AbdessamiiOukalrazqou	3fccfba900	[gen_from_riscv_config]modify csr updater.py /fix-2191 , modify csr_updater.yaml (#2258)	2024-06-14 10:51:37 +02:00
AbdessamiiOukalrazqou	e0da6e3569	Fix access issues for reserved fields (#2187)	2024-06-03 15:54:10 +02:00
André Sintzoff	4df326e13c	utils.py: format and fix typos (#2163)	2024-05-29 09:37:46 +02:00
AbdessamiiOukalrazqou	8fbfe3e57a	add gen from riscv config software (#2156)	2024-05-27 18:01:56 +02:00