Commit graph

20 commits

Author SHA1 Message Date
Michael Schaffner
35cfa8e884
Add simulation feature for openpiton that exposes the retired PCs. 2018-10-26 19:27:17 +02:00
Florian Zaruba
0d0f2682b8
Split frontend modules to separate files 2018-09-11 18:34:25 +02:00
Luis Vitorio Cargnini
183343b966 added the additional files into the yaml file.
Changes to be committed:
	modified:   src_files.yml
2018-09-10 14:18:20 -07:00
Michael Schaffner
cca0d66fab switch to common_cells repo, remove redundant files, cleanup + benderize 2018-08-24 16:22:49 +02:00
Florian Zaruba
238dbf8f04
Merge remote-tracking branch 'origin' into ariane_next 2018-08-21 20:22:31 -07:00
msfschaffner
8f0b388ecb Cache hierarchy and LSU load unit optimizations
* ♻️ restructure hierarchy (move dcache out into ariane/std_cache_subsystem)
* update uvm-components submodule
* ♻️ switch to newer (and better) fifo implementation. redesign of lsu_arbiter to improve on timing.
* ♻️ restructure hierarchy (move dcache out into ariane/std_cache_subsystem)
* ♻️ move icache out to cache_subsystem. connect icache performance counter.
* ♻️ code cleanup
* ♻️ rewrote sign extension mux to decrease comb. delay
* provision additional logic for FLW, FLH, FLB in load_unit
* code cleanup, add efficient RR arbiter with lookahead capability
* change portnames in ariane_wrapped.sv for verilator TB
2018-08-18 11:03:09 -07:00
Florian Zaruba
064c0a0ac7 🔥 Remove legacy if stage 2018-08-01 02:59:08 +02:00
Florian Zaruba
b21e43bc21
👾 Fix synthesis warning, update debug files 2018-07-31 01:12:18 +02:00
Florian Zaruba
0683cedce3
Adapt src_files.yml to reflect src file changes 2018-03-21 09:45:41 +01:00
Florian Zaruba
305e3c552a
Add Xilinx SRAMs 2017-11-13 20:07:58 +01:00
Florian Zaruba
caf8280a69
Wire-up machine mode interrupt request 2017-11-03 11:34:05 +01:00
Florian Zaruba
d8c047a5fb
Update src_files to include dcache 2017-11-01 18:46:44 +01:00
Florian Zaruba
d87ccef3f7 Add register file to gf22 target for synthesis 2017-07-26 09:57:09 +02:00
Florian Zaruba
a8b20fe460 Add debug_unit.sv to src_files.yml 2017-07-19 17:20:59 +02:00
Florian Zaruba
f1d5b4933c Use FF based regfile for FPGA 2017-07-16 20:19:41 +02:00
Florian Zaruba
98700454be Rename ariane_pkg to standalone compilations unit 2017-07-16 18:15:36 +02:00
Florian Zaruba
c68a215f41 Change mode of src_files.yml 2017-07-05 15:14:38 +02:00
Florian Zaruba
ac6eda5822 Adapt src_files.yml 2017-07-05 12:22:49 +02:00
Florian Zaruba
6092f683c0 Update src_files.yml 2017-07-03 17:35:47 +02:00
Florian Zaruba
463ef18a5b Add src_files.yml 2017-06-25 19:33:53 +02:00