Zbigniew Chamski
5c3e3d4545
Add GCC toolchain builder. Update README and .gitignore accordingly. ( #1415 )
2023-09-14 23:44:00 +02:00
Côme Allart
e7316aa331
add tools to gitignore
2023-09-08 17:10:29 +02:00
Florian Zaruba
dc103cd49f
Clean-up README.md and top-level directory ( #1318 )
...
* Clean-up README.md and top-level directory
This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Re-name icache req/rsp structs
The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
---------
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
2023-07-28 08:32:48 +02:00
Nils Wistoff
542f92baa7
Update Bender.yml following the common_cell vendorization ( #1101 )
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: Nicole Narr <narrn@student.ethz.ch>
Co-authored-by: Jannis Schönleber <joennlae@gmail.com>
2023-03-07 18:24:23 +01:00
cathales
215b45037e
manage all HW config parameters ( #1047 )
2023-02-07 23:35:38 +01:00
Gchauvon
e197b445fc
Add cv-x-interface ( #780 )
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* Add top hierarchy modification and rs3 for general purpose register file
* CVA6 core modifications to enable CoreV-eXtension-Interface feature
* Addition of an example coprocessor to use with CoreV-eXtension-Interface functionnalities on CVA6
* CoreV-eXtension-Interface available for FPGA
* Add work directories to gitignore
* Flist: fix cvxif files
* CVXIF: Modification and bugfix for cvxif feature
* CVXIF: simplify destination register feature
* Make 3rd read port on regfile configurable
* example_copro: use fifo_v3 instead of stream_fifo
* Makefile: compilation copro using defines
* ariane_pkg,riscv_pkg: add parameter to en/disable cvxif
* cva6.sv, ariane.sv: add hierarchy between ariane and cva6
* Clean Up code and typo
* CVXIF: moved combinatorial part to cvxif_fu module in ex_stage
* instr_decoder: rename instr predecoder and package
* Clean Up code and typo
* cvxif modification to follow style guideline
* issue_read_operands.sv: fix always_ff block for cvxif functionnal uni
2021-12-22 12:31:56 +01:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU ( #725 )
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* Initial repository re-organization (#662 )
Initial attempt to split core from APU.
Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>
Compile `corev_apu` (#667 )
* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Add extended verification support (#685 )
* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6
according to variant variable
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* add RVFI tracer and debug support
New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv
- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Move example_tb from cva6 to core-v-verif project
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile: remove useless rule for vsim
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add timescale definition when vsim is used
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add vcs support (fix #570 )
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* rvfi_tracer.sv: fix compilation error raised by vcs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: use only 2 threads for verilator
when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Flist.cva6: cleanup for synthesis workflow
Thales synthesis workflow does not manage comments at end of lines
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Support FPGA generation
- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Create cva6_config_pkg to setup 32- or 64-bit configuration
According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* riscv_pkg.sv: clean-up the cva6_config_pkg import
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Add lfsr.sv to manifest
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Directory re-organzation
* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726 )
into the new file organisation
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729 )
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
OttG
7760227f88
Added rules for compiling and running tests on xcelium ( #620 )
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Signed-off-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
Co-authored-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
2021-02-22 10:50:00 +01:00
Florian Zaruba
a89032f96b
ci: Fix long GCC builds
...
The CI timed out many times due to overly long GCC builds (and checkouts).
This commit rectifies this issue and downloads pre-built toolchains and
Verilator builds.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
2020-08-25 12:43:36 +02:00
Florian Zaruba
3c40965e8a
Merge remote-tracking branch 'origin/ariane_next' into fpga_dev
2018-11-17 22:38:54 +01:00
Florian Zaruba
c907270502
First instructions passing on Spike
2018-11-03 22:44:45 +01:00
Florian Zaruba
95519e4a2a
Clean-up fpga folder
2018-10-29 11:53:21 +01:00
Florian Zaruba
25a0470df6
Fix Issue #127 ( #128 )
...
* Switch to AXI structs
* Fix problems with ID width mismatches
* 📝 Update CHANGELOG
2018-10-17 16:30:58 +02:00
Florian Zaruba
9d1f6b1b76
Fix multi-hart debug issues
2018-09-14 10:57:48 +02:00
Florian Zaruba
3ec61a67cc
Change build dir, adapt README
2018-07-24 18:24:45 -07:00
Florian Zaruba
527e944577
🚧 Verilator debug integration
2018-07-10 09:20:07 -07:00
Florian Zaruba
62fffe6a9a
Add correct dependencies
2018-03-06 17:20:47 +01:00
Florian Zaruba
98b924a76f
📝 Update doc add .travis.yml
2018-02-05 13:22:52 +01:00
Florian Zaruba
30b1e5f464
Add option parsing to verilator environment
2018-02-01 18:52:03 +01:00
Florian Zaruba
491ea33be4
Update riscv-torture test framework
2018-01-23 17:12:27 +01:00
Florian Zaruba
aa9d4e6642
Add CI scripts
2018-01-23 11:57:19 +01:00
Florian Zaruba
008af68b58
Start implementing Verilator wrapper
2018-01-17 19:23:05 +01:00
Florian Zaruba
492ad51c7c
Add support for device tree
...
- compiling
- loading
2017-07-13 18:05:29 +02:00
Florian Zaruba
5625728f01
Add ability to dump torture signature
2017-06-27 10:40:18 +02:00
Florian Zaruba
34976972b8
Update .gitignore
2017-06-25 18:16:11 +02:00
Florian Zaruba
aa50f69434
Adapt dcache arbiter testbench using new dcache if
2017-05-29 15:51:31 +02:00
Florian Zaruba
c1d00a43e7
💚 Fixing Scoreboard testbench after #7
2017-04-28 11:57:11 +02:00
Florian Zaruba
1f526a8c78
Doc: Reorganized documentation, generating pages
2017-04-08 12:31:59 +02:00
