mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-23 13:47:13 -04:00
eab88770ec
Integration of bitstream generation for Altera APU in general flow. * Automatic generation of IPs and sources required for Altera FPGA * Adaptation of bootrom code (UART used in Altera is different and needs a different driver) * Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users * Configuration file for openocd connection with vJTAG tap |
||
|---|---|---|
| .. | ||
| constraints | ||
| ip | ||
| src | ||
| altera.cfg | ||
| io_standard_constraints.csv | ||
| ip_files.csv | ||
| loc_constraints.csv | ||
| Makefile | ||
| search_paths.csv | ||
| settings.csv | ||