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cva6/verif/tb/core
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AEzzejjari 668829de6e
Set the environment configuration only from env_cfg constraints. (#2408)
2024-08-29 18:00:32 +02:00
..
bootrom move files to a verif directory 2023-09-07 09:50:50 +02:00
tb_components move files to a verif directory 2023-09-07 09:50:50 +02:00
custom_uvm_macros.svh Bump verif/core-v-verif from f7bda8e to NOTMERGED (#2044) 2024-05-30 15:57:58 +02:00
cva6_tb_verilator.cpp move files to a verif directory 2023-09-07 09:50:50 +02:00
Flist.cva6_tb Remove all logic and sequential related to RVFI in CORE cva6 (#1762) 2024-01-18 22:51:10 +01:00
Makefile fix regress tests and makefiles 2023-09-07 11:38:34 +02:00
README.md move files to a verif directory 2023-09-07 09:50:50 +02:00
uvma_core_cntrl_pkg.sv Bump verif/core-v-verif from f7bda8e to NOTMERGED (#2044) 2024-05-30 15:57:58 +02:00
uvma_cva6pkg_utils.sv Set the environment configuration only from env_cfg constraints. (#2408) 2024-08-29 18:00:32 +02:00
uvma_cva6pkg_utils_pkg.sv Bump verif/core-v-verif from f7bda8e to NOTMERGED (#2044) 2024-05-30 15:57:58 +02:00
uvma_rvfi_pkg.sv Bump core-v-verif d94f0de and fix questa simulator (#1915) 2024-03-21 19:02:41 +01:00
uvmc_rvfi_reference_model_pkg.sv Bump core-v-verif d94f0de and fix questa simulator (#1915) 2024-03-21 19:02:41 +01:00
uvmc_rvfi_scoreboard_pkg.sv Bump core-v-verif d94f0de and fix questa simulator (#1915) 2024-03-21 19:02:41 +01:00

README.md

Experimental Stand-alone testbench for the CVA6

This do-nothing TB supports experiments with the CVA6 to develop a standalone testbenech for the CVA6. It uses a "core-only" manifest file Flist.cva6.

Current status:

Compiles and runs without errors for a few thousand clock cycles under either Verilator, Metrics DSIM or Cadence Xcelium (xrun).

Give it a try:

$ make help