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https://github.com/openhwgroup/cva6.git
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eab88770ec
Integration of bitstream generation for Altera APU in general flow. * Automatic generation of IPs and sources required for Altera FPGA * Adaptation of bootrom code (UART used in Altera is different and needs a different driver) * Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users * Configuration file for openocd connection with vJTAG tap
1.5 KiB
1.5 KiB
| 1 | TOP_LEVEL_ENTITY cva6_altera |
|---|---|
| 2 | ORIGINAL_QUARTUS_VERSION 24.1.0 |
| 3 | PROJECT_OUTPUT_DIRECTORY output_files |
| 4 | MIN_CORE_JUNCTION_TEMP 0 |
| 5 | MAX_CORE_JUNCTION_TEMP 100 |
| 6 | DEVICE AGFB014R24B2E2V |
| 7 | ERROR_CHECK_FREQUENCY_DIVISOR 256 |
| 8 | USE_CONFIGURATION_DEVICE ON |
| 9 | GENERATE_PR_RBF_FILE ON |
| 10 | ENABLE_ED_CRC_CHECK ON |
| 11 | MINIMUM_SEU_INTERVAL 0 |
| 12 | PWRMGT_SLAVE_DEVICE_TYPE ED8401 |
| 13 | PWRMGT_SLAVE_DEVICE0_ADDRESS 47 |
| 14 | PWRMGT_SLAVE_DEVICE1_ADDRESS 00 |
| 15 | PWRMGT_SLAVE_DEVICE2_ADDRESS 00 |
| 16 | ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ |
| 17 | USE_PWRMGT_SCL SDM_IO14 |
| 18 | USE_PWRMGT_SDA SDM_IO11 |
| 19 | USE_CONF_DONE SDM_IO16 |
| 20 | AUTO_RESTART_CONFIGURATION OFF |
| 21 | USE_CVP_CONFDONE SDM_IO10 |
| 22 | DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ |
| 23 | PWRMGT_PAGE_COMMAND_ENABLE OFF |
| 24 | POWER_APPLY_THERMAL_MARGIN ADDITIONAL |
| 25 | USE_INIT_DONE SDM_IO0 |
| 26 | BOARD default |
| 27 | PLACEMENT_EFFORT_MULTIPLIER 50 |
| 28 | FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS |
| 29 | QII_AUTO_PACKED_REGISTERS SPARSE |
| 30 | OPTIMIZATION_TECHNIQUE SPEED |