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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
177 commits 16 branches 13 tags 288 MiB
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Florian Zaruba 0941bb87ec ✅ First implementation of LSU test
2017-05-02 15:48:25 +02:00
docs 📝 Add basic information on the testbenches 2017-04-28 12:32:26 +02:00
include ✅ Added UVM testbench for mem arbiter 2017-05-01 20:43:43 +02:00
src ✅ Add LSU testbench stub 2017-05-02 12:13:26 +02:00
tb ✅ First implementation of LSU test 2017-05-02 15:48:25 +02:00
uvm-scaffold@1e44fd194a ✅ First implementation of LSU test 2017-05-02 15:48:25 +02:00
.gitignore 💚 Fixing Scoreboard testbench after #7 2017-04-28 11:57:11 +02:00
.gitlab-ci.yml ✅ Add empty store queue test 2017-04-28 12:58:57 +02:00
.gitmodules Add UVM scaffolding submodule 2017-04-30 18:23:56 +02:00
CHANGELOG 📝 Add CHANGELOG to gitlab, manually created 2017-04-21 11:09:30 +02:00
CONTRIBUTING.md 👾 Fixing latches and wrong output assignment 2017-04-22 12:51:23 +02:00
LICENSE 📝 Add license 2017-04-21 11:11:40 +02:00
Makefile ✅ First implementation of LSU test 2017-05-02 15:48:25 +02:00
mkdocs.yml Removed hard link to coverage report 2017-04-09 15:28:55 +02:00
README.md 📝 Added contribution guide 2017-04-20 23:06:47 +02:00

README.md

build status coverage report

Ariane RISC-V CPU

For detailed documentation refer to the online documentation (Login: zarubaf Password: zaruba).

Contributing

Check out the contribution guide