AngelaGonzalezMarino 9877af5eb6 fix size of vectors when AxiNumWords=1 (#2639) ... in wt_axi_adapter, axi_rd_blen and axi_wr_blen are defined like this: logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen; However, if AxiNumWords=1, this gives a synthesis error. This happens if the cache line is set to 64 bits (same as AXI width). It can be fixed by changing to: logic [AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords-1:0] axi_rd_blen, axi_wr_blen;		2024-12-03 07:14:29 +01:00
..
hpdcache@edd501cc74	update the hpdcache to its latest version (#2579)	2024-11-05 23:57:20 +01:00
amo_alu.sv	verible-verilog-format: apply it on core directory (#1540)	2023-10-18 16:36:00 +02:00
axi_adapter.sv	Fix $fatal system task incorrect usage (#2619)	2024-11-20 22:22:50 +01:00
cache_ctrl.sv	cache_ctrl: Generalise AXI offset generation (#2573)	2024-11-04 09:24:57 +01:00
cva6_hpdcache_if_adapter.sv	update the hpdcache to its latest version (#2579)	2024-11-05 23:57:20 +01:00
cva6_hpdcache_subsystem.sv	update the hpdcache to its latest version (#2579)	2024-11-05 23:57:20 +01:00
cva6_hpdcache_subsystem_axi_arbiter.sv	Fix $fatal system task incorrect usage (#2619)	2024-11-20 22:22:50 +01:00
cva6_hpdcache_wrapper.sv	update the hpdcache to its latest version (#2579)	2024-11-05 23:57:20 +01:00
cva6_icache.sv	Add support for cv32a65x dedicated synthesis (#2178)	2024-06-04 10:58:09 +02:00
cva6_icache_axi_wrapper.sv	Parametrization step 3 (#1935)	2024-03-15 17:21:34 +00:00
miss_handler.sv	Verible reformat (#2014)	2024-04-08 11:26:08 +02:00
std_cache_subsystem.sv	expand glob port maps (#2585)	2024-11-07 16:51:46 +01:00
std_nbdcache.sv	Parametrization step 3 (#1935)	2024-03-15 17:21:34 +00:00
tag_cmp.sv	expand glob port maps (#2585)	2024-11-07 16:51:46 +01:00
wt_axi_adapter.sv	fix size of vectors when AxiNumWords=1 (#2639)	2024-12-03 07:14:29 +01:00
wt_cache_subsystem.sv	Move DCacheType to config struct (#2025)	2024-04-10 23:26:21 +02:00
wt_dcache.sv	Parametrization: Use CVA6Cfg.WtDcacheWbufDepth in place of DCACHE_WBUF_DEPTH (#2166)	2024-05-30 12:26:58 +02:00
wt_dcache_ctrl.sv	Define InstrTlbEntries, DataTlbEntries, cfg.NrLoadPipeRegs, NrStorePipeRegs, DcacheIdWidth as CVA6 parameters (#2034)	2024-04-12 09:06:35 +02:00
wt_dcache_mem.sv	Add support for cv32a65x dedicated synthesis (#2178)	2024-06-04 10:58:09 +02:00
wt_dcache_missunit.sv	use dcache_assoc_width (#2640)	2024-12-02 17:40:38 +01:00
wt_dcache_wbuffer.sv	Parametrization: Use CVA6Cfg.WtDcacheWbufDepth in place of DCACHE_WBUF_DEPTH (#2166)	2024-05-30 12:26:58 +02:00
wt_l15_adapter.sv	Parametrization step 3 (#1935)	2024-03-15 17:21:34 +00:00