The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Find a file
Côme Allart 5944f1d581 ci: refactor job descriptions
Each job needs less code in cva6.yml

It also fixes an issue in CVV pipelines, where the CVA6 hash in the
dashboard was not the one used in some jobs of the pipeline.
2023-07-27 10:14:31 +02:00
.github add license header to dashboard-done.yml 2023-05-11 11:47:34 +02:00
.gitlab-ci ci: refactor job descriptions 2023-07-27 10:14:31 +02:00
bin Hotfix for security alert 2023-04-11 07:54:02 -04:00
core-v-cores Create .gitignore 2020-03-12 11:33:14 -05:00
cv32e40p Fix copyright year 2023-03-29 13:33:59 -04:00
cv32e40s Fix copyright year 2023-03-29 13:33:59 -04:00
cv32e40x Fix copyright year 2023-03-29 13:33:59 -04:00
cva6 Merge pull request #2078 from ThalesSiliconSecurity/test_isa 2023-07-26 14:56:20 +02:00
docs Update cva6/dev from master 2023-04-28 15:27:18 +02:00
lib HOTFIX : Removing rd from cross 2023-07-21 15:38:51 +02:00
mk Merge pull request #1668 from MikeOpenHWGroup/dpi_dasm_4_vcs 2023-04-18 11:58:20 -04:00
tools/vptool [VPTOOL] Improve Python dependency handling, update DV plan launch scripts. 2023-02-27 12:20:16 +01:00
util Add vendoriztaion toolkit to core-v-verif. 2023-05-15 23:46:11 +02:00
vendor Update spike for cus_exc: 2023-07-11 09:24:46 +02:00
vendor_lib Latest change for debug priorities 2021-12-09 15:14:01 +00:00
.gitignore Enhance quick_start guide 2023-03-21 12:20:17 +00:00
.gitlab-ci.yml ci: refactor job descriptions 2023-07-27 10:14:31 +02:00
.metrics.json Fixed typos for image name 2022-02-02 21:21:43 -05:00
.readthedocs.yaml [skip ci] python requirements location for RTD 2022-06-08 16:40:14 -04:00
CODE_OF_CONDUCT.md Create CODE_OF_CONDUCT.md 2020-01-21 14:53:10 -05:00
CONTRIBUTING.md Add branching information to the CONTRIBUTING readme 2021-03-15 12:55:59 -05:00
GitCheats.md [skip ci] Fix formatting 2022-06-23 10:43:35 -04:00
LICENSE.md Make words in italics match those on the Solderpad website 2019-11-30 16:04:29 -06:00
MergeTest.md Minor cleanup 2021-03-03 14:10:46 -05:00
NEWS_ARCHIVE.md Extract the news 2021-02-22 16:46:40 -05:00
README.md [skip ci] Point to Ad free version of VerifStrat 2022-06-08 16:55:59 -04:00

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Getting Started

First, have a look at the OpenHW Group's website to learn a bit more about who we are and what we are doing.
For first time users of CORE-V-VERIF, the Quick Start Guide in the CORE-V-VERIF Verification Strategy is the best place to start.

Directory Structure of this Repo

bin

Various utilities for running tests and performing various verification-related activities in the core-v-verif repository.

core-v-cores

Empty sub-directory into which the RTL from one or more of the CORE-V-CORES repositories is cloned.

cv32e40p, cv32e40x, cv32e40s, cva6

Core-specific verification code.

docs

Sources for the Verification Strategy document, DV plans, coding style guidelines and available coverage reports.

mk

Common simulation Makefiles that support testbenches for all CORE-V cores.

lib

Common components for the all CORE-V verification environments.

vendor_lib

Verification components supported by third-parties.

Contributing

We highly appreciate community contributions. You can get a sense of our current needs by reviewing the GitHub projects associated with this repository. Individual work-items within a project are defined as issues with a task label.

To ease our work of reviewing your contributions, please:

  • Review CONTRIBUTING and our SV/UVM coding style guidelines.
  • Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
  • Write meaningful commit messages.
  • If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.