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cva6/src
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Nils Wistoff 6865f71d56
Fix modelsim flow (#619) 
fixes issues with the modelsim flow introduced by recent commits.
* riscv_pkg, csr_regfile: explicit typecast of satp.mode to vm_mode_t
* ariane_testharness: axi_adapter.type_i is of type ariane_axi::ad_req_t

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2021-02-19 18:31:53 +01:00
..
axi@3f5d5b540a Bump axi submodule to v0.7 and fix include path for registers.svh in run.tcl 2019-06-04 10:36:17 +02:00
axi_mem_if@4650ca9006 Merge branch 'master' into ariane_next 2018-07-20 21:33:23 -07:00
axi_node@a29a69a543 Add Exclusive Adapter (#187) 2019-03-18 11:51:58 +01:00
axi_riscv_atomics@550881f12e Improve Tandem Simulation, switch-able caches and fix a cache-bug (#192) 2019-03-18 11:51:58 +01:00
cache_subsystem cache_ctrl: Remove forward reference (#600) 2021-01-31 10:03:03 +01:00
clint Fix Verific comparability (#613) 2021-02-17 07:58:09 +01:00
common_cells@b2a4b2d3de ariane: Support less than 2 commit ports (#365) 2020-04-15 09:46:15 +02:00
fpga-support@a3ba269c0f Improve Spike - Ariane alignment 2018-11-04 16:20:19 +01:00
fpu@79f75e0a0f fpu: Bump to release 0.6.2 2020-06-02 19:09:27 +02:00
frontend Fix Verific comparability (#613) 2021-02-17 07:58:09 +01:00
pmp Fix Xcelium compatibility (#614) 2021-02-18 11:17:33 +01:00
register_interface@d8aeccc65f rv_plic: Add lowrisc PLIC 2019-06-04 10:36:17 +02:00
riscv-dbg@6d768ac637 Bump FPU, DM and common cells 2019-06-04 10:36:17 +02:00
rv_plic@ebe3e98889 openpiton_periphs: Integrate rv_plic 2019-06-04 10:36:17 +02:00
tech_cells_generic@ffe7818dc2 Improve testability of debug module 2018-09-29 18:41:44 +02:00
util Flush all state when reset is not deasserted (#607) 2021-02-16 10:53:42 +01:00
alu.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
amo_buffer.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
ariane.sv lint: Fix synthesis tool warnings (#564) 2020-12-16 19:52:24 +01:00
ariane_regfile.sv Update ariane_regfile.sv 2018-10-15 10:01:49 +02:00
ariane_regfile_ff.sv Fix regfile again 2018-09-18 15:04:47 +02:00
axi_adapter.sv axi_adapter/shim: Only use incr burst type (#595) 2021-01-28 08:23:07 +01:00
axi_shim.sv axi_adapter/shim: Only use incr burst type (#595) 2021-01-28 08:23:07 +01:00
branch_unit.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
commit_stage.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
compressed_decoder.sv cva6: Remove global imports (#489) 2020-08-26 12:40:06 +02:00
controller.sv cva6: Remove global imports (#489) 2020-08-26 12:40:06 +02:00
csr_buffer.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
csr_regfile.sv Fix modelsim flow (#619) 2021-02-19 18:31:53 +01:00
decoder.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
dromajo_ram.sv dromajo_ram: Fix IEEE compliance (#584) 2021-01-18 10:36:22 +01:00
ex_stage.sv lint: Fix synthesis tool warnings (#564) 2020-12-16 19:52:24 +01:00
fpu_wrap.sv cva6: Remove global imports (#489) 2020-08-26 12:40:06 +02:00
id_stage.sv frontend: Clean-up instruction frontend 2019-06-04 10:36:17 +02:00
instr_realign.sv cva6: Remove global imports (#489) 2020-08-26 12:40:06 +02:00
issue_read_operands.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
issue_stage.sv lint: Fix size mismatches and parameterisation (#524) 2020-10-07 09:57:58 +02:00
load_store_unit.sv lint: Fix synthesis tool warnings (#564) 2020-12-16 19:52:24 +01:00
load_unit.sv load_unit: fix exception forwarding 2020-12-01 14:58:45 +01:00
mmu.sv lint: Fix synthesis tool warnings (#564) 2020-12-16 19:52:24 +01:00
mult.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
multiplier.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
perf_counters.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
ptw.sv lint: Fix synthesis tool warnings (#564) 2020-12-16 19:52:24 +01:00
re_name.sv cva6: Remove global imports (#489) 2020-08-26 12:40:06 +02:00
scoreboard.sv Fix Verific comparability (#613) 2021-02-17 07:58:09 +01:00
serdiv.sv cva6: Remove global imports (#489) 2020-08-26 12:40:06 +02:00
store_buffer.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
store_unit.sv cva6: Make xlen configurable (#459) 2020-09-10 10:59:14 +02:00
tlb.sv lint: Fix size mismatches and parameterisation (#524) 2020-10-07 09:57:58 +02:00