mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-24 14:17:16 -04:00

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Find a file

Florian Zaruba c2a275e6f1 Reduce number of cores for CI build		2018-02-05 17:34:46 +01:00
ci	Reduce number of cores for CI build	2018-02-05 17:34:46 +01:00
docs	Remove old and merged documentation	2018-01-25 10:58:04 +01:00
failedtests	Update riscv-torture test framework	2018-01-23 17:12:27 +01:00
include	Use generic memories in icache	2018-01-25 17:07:28 +01:00
riscv-torture@4e1c13adc5	Clean-up add github remotes to submodules	2018-01-26 10:15:53 +01:00
src	Pump axi_slice version	2018-02-05 13:49:53 +01:00
tb@d2c8a8a977	Pump TB version	2018-02-02 15:01:41 +01:00
.editorconfig	📝 Update doc add .travis.yml	2018-02-05 13:22:52 +01:00
.gitignore	📝 Update doc add .travis.yml	2018-02-05 13:22:52 +01:00
.gitlab-ci.yml	📝 Update doc add .travis.yml	2018-02-05 13:22:52 +01:00
.gitmodules	📝 Update doc add .travis.yml	2018-02-05 13:22:52 +01:00
.travis.yml	Update travis build environment	2018-02-05 17:29:08 +01:00
ariane-run-torture	🐛 Resolve bug emerging from merge	2017-12-17 16:57:37 +01:00
Bender.yml	Add option parsing to verilator environment	2018-02-01 18:52:03 +01:00
CHANGELOG.md	Remove execute permissions from source files	2018-01-26 10:31:49 +01:00
CONTRIBUTING.md	Update headers and style guide	2018-01-18 17:45:00 +01:00
LICENSE	Add SolderPad Hardware License	2018-01-16 10:07:39 +01:00
Makefile	Add option parsing to verilator environment	2018-02-01 18:52:03 +01:00
README.md	Update axi_node subrepo to tracker github master	2018-02-05 13:33:30 +01:00
src_files.yml	Add Xilinx SRAMs	2017-11-13 20:07:58 +01:00

Ariane RISC-V CPU

Getting Started

Go and get the RISC-V tools.

Checkout the repository and initialize all submodules

git checkout https://github.com/pulp-platform/ariane.git
git submodule update --init --recursive

Build the Verilator model of Ariane by using the Makefile:

make verilate