Florian Zaruba 8de6e35288 ci: Consolidate tests ... The tests have been spread to many smaller tests previously to avoid CI timeouts. With memory preloading the overhead of setting up the tests is dominating so we merge the tests again. Also remove `rv64ui-v-fence_i` from test list as it is currently failing. Signed-off-by: Florian Zaruba <florian@openhwgroup.org>		2020-08-25 12:43:36 +02:00
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build-riscv-gcc.sh	Fix travis cache path	2019-01-08 15:05:35 +01:00
build-riscv-tests.sh	Merge remote-tracking branch 'origin/ariane_next' into fpga_dev	2018-11-17 22:38:54 +01:00
check-tests.sh	Add System Verilog FPU (#163)	2019-03-18 11:51:58 +01:00
default.config	Merge remote-tracking branch 'upstream/ariane_next' into serpent	2018-11-21 20:15:32 +01:00
float.config	Add System Verilog FPU (#163)	2019-03-18 11:51:58 +01:00
get-torture.sh	Scoreboard refactoring for better timing	2019-06-04 10:36:17 +02:00
gitlab-ci-emul.sh	Add missing Ubuntu package to ci-emul scripts.	2018-11-18 11:33:47 +01:00
install-dtc.sh	Minor modifications to ci scripts.	2018-11-02 18:02:07 +01:00
install-spike.sh	fesvr: Remove legacy repo and update Spike	2020-08-25 12:43:36 +02:00
install-verilator.sh	Update changelog and fix potential bug in install-verilator script	2019-06-04 10:36:17 +02:00
make-tmp.sh	Change shebang of CI scripts	2018-02-06 13:08:54 +01:00
path-setup.sh	Update to Verilator 4.014	2019-06-04 10:36:17 +02:00
riscv-amo-tests.list	Misc majurity fixes (#125)	2018-10-17 11:57:18 +02:00
riscv-asm-tests.list	ci: Consolidate tests	2020-08-25 12:43:36 +02:00
riscv-benchmarks.list	ci: Fix long GCC builds	2020-08-25 12:43:36 +02:00
riscv-fp-tests.list	fpu: Add distributed pipe regs to ease FPGA timing	2019-06-04 10:36:17 +02:00
riscv-mul-tests.list	verilator: Add memory preloading	2020-08-25 12:43:36 +02:00
torture_make.patch	Minor modifications to ci scripts.	2018-11-02 18:02:07 +01:00
travis-ci-emul.sh	Add missing Ubuntu package to ci-emul scripts.	2018-11-18 11:33:47 +01:00