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cva6/verif/sim
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valentinThomazic fd12ee596c
Add smoke-tests and fpga logs on dashboard (#1928)
2024-03-14 14:43:56 +01:00
..
dv@f0c570d112 Convert DV into a submodule (#1591) 2023-11-03 11:20:08 +01:00
cov-exclude-mod.lst Code coverage : Exclude unread module form CC (fix issue #1903) (#1907) 2024-03-08 18:35:01 +01:00
cva6-simulator.yaml move files to a verif directory 2023-09-07 09:50:50 +02:00
cva6.hvp Map AXI functional coverage to the HVP (#1867) 2024-02-23 18:04:58 +01:00
cva6.py Add smoke-tests and fpga logs on dashboard (#1928) 2024-03-14 14:43:56 +01:00
cva6.yaml Add priv level to cva6.py and fix smoke-tests (#1768) 2024-01-17 23:14:19 +01:00
cva6_base_testlist.yaml remove hard-coded gcc options (#1652) 2023-11-23 23:35:20 +01:00
cva6_spike_log_to_trace_csv.py Spike Tandem Implementation using VCS simulator (#1561) 2023-11-09 19:29:24 +01:00
init_run_uvm_fsdb.do move files to a verif directory 2023-09-07 09:50:50 +02:00
init_run_uvm_vpd.do move files to a verif directory 2023-09-07 09:50:50 +02:00
init_uvm.do move files to a verif directory 2023-09-07 09:50:50 +02:00
link.ld move files to a verif directory 2023-09-07 09:50:50 +02:00
Makefile Generate separate per-target logs when simulating. (#1870) 2024-03-05 19:37:57 +01:00
setup-env.sh Improve environment setup. Fix Verilator installation process. (#1864) 2024-03-05 17:18:33 +01:00
verilator_log_to_trace_csv.py move files to a verif directory 2023-09-07 09:50:50 +02:00