Tobias Wölfel
912d6da1c2
Update description for running RISC-V compliance
...
The RISC-V compliance test system requires an absolute path to the
executable or one which starts at `riscv-test-suite/*`.
2019-10-08 15:22:37 +02:00
udinator
84664077ee
[DV] Top level toggle coverage ( #371 )
2019-10-04 16:36:47 -07:00
Philipp Wagner
f54dfe5d4b
RISC-V Compliance test: Enable tracing
...
Use the tracing-enabled core wrapper when executing the RISC-V
compliance test suite to help with debugging it.
2019-10-03 09:42:45 +01:00
udinator
48e604ab9e
[DV] Update ibex log regex ( #366 )
2019-10-02 13:16:47 -07:00
udinator
f2048ea8e4
[DV] Debug single step test ( #362 )
2019-10-01 16:39:32 -07:00
taoliug
b03ae4e2a7
[DV]Add Makefile target for functional coverage ( #358 )
2019-09-30 10:24:44 -07:00
udinator
074e637b11
[DV] Fix ovpsim compare issue ( #355 )
...
* [DV] Fix ovpsim compare issue
* Update some test descriptions to avoid timeouts, update debug test
2019-09-27 17:45:58 -07:00
udinator
1615969bc1
[DV] Refactor debug stress stimulus to avoid race conditions ( #354 )
2019-09-25 19:08:05 -07:00
udinator
576d0ed76d
[DV] Basic performance test ( #352 )
2019-09-25 16:28:57 -07:00
udinator
6bae3f2d6f
Tighten debug stimulus assertion ( #351 )
2019-09-25 14:45:00 -07:00
udinator
ec02461b4a
[DV] Fix implemented_csr[] compile issue ( #346 )
2019-09-23 17:49:40 -07:00
udinator
9b967a5d97
[DV] Update implemented CSRs ( #345 )
2019-09-23 15:59:10 -07:00
udinator
717bf1ae02
Fix memory error test logic ( #344 )
2019-09-23 15:32:20 -07:00
udinator
8d799e526b
[DV] Illegal instruction monitoring ( #338 )
2019-09-19 10:45:28 -07:00
udinator
e9949f9808
[DV] Shorten length of interrupt tests to prevent timeouts ( #337 )
2019-09-19 10:19:56 -07:00
udinator
66410f6c90
[DV] Drive external stimulus to 0 after reset ( #334 )
2019-09-19 08:30:02 -07:00
udinator
e694fa05b9
Add memory error testing ( #330 )
2019-09-18 13:26:56 -07:00
Philipp Wagner
76f4db5155
Compliance test suite: Prefer D over I accesses
...
Give higher priority to data accesses from the CPU to improve
performance. This is the recommended setup for Ibex.
The test utility host needs still higher priority, otherwise the CPU
takes all bus capacity (the downside of strict priority arbitration).
2019-09-18 11:07:37 +01:00
taoliug
47acadc969
Consolidate the script logging ( #329 )
2019-09-17 16:41:43 -07:00
taoliug
e7123f1c2d
Add dsim support ( #328 )
2019-09-17 16:18:05 -07:00
udinator
80e231dd8b
Add interrupt testing, and update some debug test checks ( #324 )
2019-09-16 16:58:28 -07:00
taoliug
369f56bad0
Integrate with the new riscv-dv user extension flow ( #323 )
2019-09-16 15:06:36 -07:00
Philipp Wagner
87e50a62a9
ibex_riscv_compliance: Adjust to simutil_verilator
...
Now that verilated_toplevel.h always generates the right class we don't
need to call VERILATED_TOPLEVEL() any more.
2019-09-16 14:53:54 +01:00
Philipp Wagner
7a0614a1d0
simutil_verilator: Always produce toplevel class
...
Previously, verilated_toplevel.h contained a macro, VERILATED_TOPLEVEL()
to produce a class TOPLEVEL (whatever the toplevel happens to be). This
required all compilation units referring to that TOPLEVEL class to call
the macro.
After this change, the class is always generated in
verilated_toplevel.h. For that to work, a new define TOPLEVEL_NAME must
be globally set (e.g. passed to the compiler with -DTOPLEVEL_NAME=xxx).
2019-09-16 14:53:54 +01:00
Greg Chadwick
9958d30063
[DV] Fix latch in simple bus
...
Fixes #297
2019-09-16 13:36:23 +01:00
taoliug
0667c14f15
[DV] Standardize logging, allow parallel simulation ( #315 )
2019-09-15 12:16:14 -07:00
taoliug
7280301369
Fix ELF section name ( #314 )
2019-09-13 16:11:41 -07:00
taoliug
54eb5c2456
Fix regression failure ( #313 )
2019-09-13 16:02:34 -07:00
Philipp Wagner
6b03bc6326
Run clang-format on all source files
2019-09-11 12:00:49 +01:00
udinator
ac22439374
Update slave_driver grant timing to pass Ibex assertion checks ( #295 )
2019-09-09 14:31:29 -07:00
Greg Chadwick
bec84ca2b1
Add core_sleep_o to ibex interface
...
Signals the core is totally idle (WFI with no outstanding memory
transactions). Fixes #258
2019-09-06 08:44:48 +01:00
udinator
e9c2b2ecb3
Added dret and ebreak tests ( #281 )
2019-09-04 16:14:41 -07:00
Greg Chadwick
d14312c3cc
Replace cluster_id/core_id with hart_id ( #29 )
...
If you're migrating from the previous interface you can use
logic [31:0] hart_id;
assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};
...
ibex_core #(
...
) u_core (
...
// replace core_id_i and cluster_id_i
.hart_id_i(hart_id),
...
);
2019-09-03 14:18:39 +01:00
udinator
68b170638a
Update interrupt mode, add debug mode WFI test ( #268 )
2019-08-28 10:00:36 -07:00
udinator
2421472395
Integrate risc-v stream generator handshake into Ibex sim flow ( #264 )
2019-08-26 15:18:30 -07:00
Philipp Wagner
399f0b7e77
Update documentation how to run riscv-compliance
...
Upstream has now included ibex support, we don't need to use a custom
fork any more. Update the documentation for that.
Fixes #214
2019-08-22 23:27:13 +01:00
taoliug
03df591266
Make mtvec writable, remove previous workaround ( #256 )
2019-08-21 18:16:51 -07:00
taoliug
2601e8d898
Test cleanup ( #255 )
2019-08-21 17:19:16 -07:00
udinator
9311b25fdb
Consolidate some debug generation options, and make the signature_addr handshake optional ( #253 )
2019-08-21 11:00:17 -07:00
udinator
3bc83365ef
Add more debug tests ( #251 )
2019-08-20 11:03:15 -07:00
udinator
e4260dd075
Add basic debug test and modify sim flow ( #243 )
2019-08-15 11:18:07 -07:00
taoliug
0e91a30496
[DV] Enable aligned load/store test ( #242 )
...
* Add unaligned load/store test
* Enable unaligned load/store test, remove obsolete files
2019-08-14 17:41:13 -07:00
taoliug
9309621f04
Fix the verbose logging issue, fix coverage/waveform options ( #235 )
2019-08-13 10:23:07 -07:00
udinator
9a231c9ba6
update ibex testbench ( #232 )
2019-08-12 13:14:07 -07:00
udinator
27bd4e73d9
update ibex simulation flow ( #233 )
2019-08-09 15:49:46 -07:00
Tom Roberts
44b033cf8b
[rtl] Add support for instruction fetch errors
...
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
2019-08-09 10:44:37 +01:00
Philipp Wagner
e5bdf1ea9f
Document register map of compliance test system
2019-08-06 11:48:50 +01:00
taoliug
50f8cbd463
Fix waveform/coverage dump mode ( #215 )
2019-08-05 14:42:00 -07:00
Philipp Wagner
24a9c64bf1
Add simulation for RISC-V compliance testing
...
This adds a Verilator simulation of Ibex for use in RISC-V Compliance
Testing. In addition to ibex itself, the simulation contains a RAM and
a memory-mapped helper module for the test software to interact with the
outside world. The test framework uses this to dump a "test signature",
which is written to a certain part of the memory, and to end the
simulation. (In the future, this could be extended to include printf()
like functionality.)
2019-08-05 15:49:15 +01:00
Philipp Wagner
b72f5db6bd
DV: Add verilator simulation utility
2019-08-05 15:49:15 +01:00
