This commit replaces all X assignments in the RTL with defined
values. In addition, SystemVerilog Assertions are added to catch
invalid signal values in simulation. A new file containing the
corresponding assertion macros is added as well.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- Add the minimum amount of trigger system to support GDB hbreak
- Only a single trigger is implemented
- Only instruction address matching
- Only break into debug mode (no native debug)
- Fixes#382
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The VerilatorSimCtrl class was always intended to be used only once in
an application, since it sets up a global signal handler and needs to be
accessible from DPI modules. This accessibility was achieved through a
global variable `simctrl`.
With this commit the VerilatorSimCtrl is switched to a singleton class.
The instance is accessible through `VerilatorSimCtrl::GetInstance()`.
The downside of that approach is that we loose the constructor
arguments, and need to deal with a class which potentially hasn't top or
the clock and reset signals set.
All functions in simutil_verilator return booleans to indicate
success/failure, where 1 == true, and 0 == false.
simutil_verilator_set_mem() returns an int due to DPI interface
restrictions. Before, 0 meant success, and 1 meant error.
To keep things nice and consistent, turn things around and align with
the bool meaning.
Support initialization of memory by loading content from ELF files.
All segments of the ELF file with the type `PT_LOAD` are merged into a
temporary buffer and then forwarded to a predefined memory.
This is an addition for setting the memories with VMEM files.
Memories must implement `simutil_verilator_set_mem` to support the
setting of values with a width of 32 bits. A return value of 0 must
indicate a successful operation and 1 an error.
Memories are defined by a call to `RegisterMemoryArea()` before the
execution of the simulation, at which point the arguments are parsed and
the initialization is started. The memories are identified by unique
name. The design specific location is used to set the SystemVerilog
scope.
Registered memories can be printed by using `-l list`. The unique name
is used for `-l name,file.elf` together with the file path.
An optional part of the argument is the type of the file, `elf` or
`vmem`, and if not provided it is attempted to detect the type by
looking at the file extension.
The memory specific arguments which already existed accept now also ELF
files. They use predefined names and are included to keep the interface
stable.
Contents of an ELF segment which has a bigger memory size than file size
are not set. This is typically required for BSS sections for zero-ing
the memory.
- Switch from Makefile calling fusesoc to fusesoc calling Makefile
- Pass parameters through DPI rather than as env variables
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
All CSR addresses supported by the TB are now delared as an X
macro list. This list is then used to autogenerate the enum
type, string print helper and an array of all addresses.
The array of addresses can now be used by the randomize generator
to turn an arbitrary integer index into an address. This removes
the restriction on only generating contiguous address ranges noted
in #443.
Add missing signal csr_restore_dtret_i
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit removes a copy of the dummy clock gating primitive from
tree previously used for UVM-based DV. There is another, identical copy
of the same primitive in `shared/rtl` that can be used instead.
This resolveslowRISC/ibex#213.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
