Commit graph

522 commits

Author SHA1 Message Date
taoliug
54fac2954a
Move DV README.md to doc/verification.rst (#208) 2019-08-02 15:05:02 -07:00
taoliug
584ceda381 Add README.md for the DV flow (#207) 2019-08-02 13:45:33 -07:00
taoliug
463f518424 Integrate with new end-to-end simulation (#206) 2019-08-02 08:31:12 -07:00
taoliug
511b205226
Enable WFI test in regression (#190) 2019-07-24 13:52:00 -07:00
taoliug
2bf1ab923a
Fix interrtup test (#189)
Update TB for the new interrupt interface
2019-07-24 11:46:18 -07:00
Pirmin Vogel
72c77f855d Remove legacy interrupt controller
This removal got partially lost while rebasing for PR #149.
2019-07-24 15:57:36 +01:00
Philipp Wagner
62f3573f2b Rework how tracer is instantiated and called
This change is slighly painful, but a necessary cleanup around the
tracer.

- We now provide a separate core file for the tracer, called
  "ibex_tracer.core" (in line with "ibex_tracer.sv"). The core is called
  "lowrisc:ibex:ibex_tracer".
- The toplevel wrapper with tracing enabled got renamed to
  "ibex_core_tracing.sv", and the core file is correspondingly called
  "ibex_core_tracing.core. The core in it is called
  "lowrisc:ibex:ibex_core_tracing".
- Finally to keep symmetry, the toplevel of Ibex itself got renamed in
  the core file from "lowrisc:ibex:ibex" to "lowrisc:ibex:ibex_core".
  This ensures that we have the same name for the core file, the source
  entry point, and the core name.

IMPORTANT NOTE:
If you apply this change and use fusesoc, you need to adjust the name of
the core dependency from "lowrisc:ibex:ibex" to
"lowrisc:ibex:ibex_core".
2019-07-23 19:45:48 +01:00
taoliug
bc61f0bfd9
Fix compile issue caused by design changes (#179) 2019-07-19 18:01:12 -07:00
taoliug
c96ece0429
fix ibex regression script (#165) 2019-07-16 17:56:39 -07:00
taoliug
30f2d6db64
debug mode related TB updates (#160) 2019-07-15 16:36:18 -07:00
taoliug
4eaa57041d
fix debug_seq runtime options, update trace processing script (#158) 2019-07-15 13:25:15 -07:00
taoliug
98cfad26f3
Use new ibex_core_tracer as DUT (#148) 2019-07-11 19:35:47 -07:00
taoliug
b0d2c0ff48
Add support for debug mode and interrupt test (#146) 2019-07-11 11:19:06 -07:00
{“Tao
205db5e6ea Change return to exit in sim script (fixes #137) 2019-07-11 16:39:02 +01:00
taoliug
b203a0f7c7
Add bash shebang to sim script(fixes #133) (#135) 2019-07-10 23:13:21 -07:00
taoliug
6d09fb1060
Add interrupt agent (#116) 2019-07-01 18:25:37 -07:00
taoliug
2d66834f14
Integrate riscv-dv upstream changes (#107)
* Remove all local patches

* Update google_riscv-dv to 00739df

Update code from upstream repository https://github.com/google/riscv-
dv to revision 00739df0ec744986934097bebcde3ebf5a4fdf81

* Merge pull request #30 from google/dev (taoliug)
* Fix LSF options (Tao Liu)
* Refactoring to make extension easier (Tao Liu)
* Merge pull request #29 from google/dev (taoliug)
* Add a sample program (Tao Liu)
* Merge pull request #28 from google/dev (taoliug)
* Move riscv_core_setting to a separate folder (Tao Liu)
* Merge pull request #27 from google/dev (taoliug)
* Add ebreak/wfi test, more regression control (Tao Liu)
* Merge pull request #26 from google/dev (taoliug)
* Add support for GPR based comparison (Tao Liu)

* Add ibex extensions for riscv_dv
2019-07-01 08:59:31 -07:00
Pirmin Vogel
2ed71a499a Make dummy clock gating module compatible with latch-based reg file
The latch-based register file needs a clock gating cell that is
transparent for the clock enable signal only during the low clock
phase.
2019-06-26 14:09:23 +01:00
taoliug
cc8aed4ed2
Fix tcl path (#73) 2019-06-07 15:01:19 -07:00
taoliug
52bc23cc39
Add coverage dump options (#71) 2019-06-07 13:58:06 -07:00
taoliug
50c73dcf58
fix ibex TB top compilation issue (#58) 2019-06-04 10:55:22 -07:00
taoliug
2782ae9677 Add UVM testbench
This adds a UVM testbench and associated tooling for Ibex. 
The tooling requires Synopsys VCS to run.
2019-06-03 16:45:00 +01:00