Move Xilinx specific code into shared folder so it can be re-used by
different examples.
Use the shared RAM code and make use of byte enable signal.
Fixeslowrisc/ibex#144
Simple system is a basic verilator top-level testbench for running
executables. It has functionality for outputting text to a log file
and for the software to terminate the simulation
This testbench was helpful in creating the initial tracer, but is not
fully working any more, and too limited to test the trace fully.
Extending it is inconvenient, as the creation of instruction sequences
through the bus interface is easy to get wrong.
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
This change is slighly painful, but a necessary cleanup around the
tracer.
- We now provide a separate core file for the tracer, called
"ibex_tracer.core" (in line with "ibex_tracer.sv"). The core is called
"lowrisc:ibex:ibex_tracer".
- The toplevel wrapper with tracing enabled got renamed to
"ibex_core_tracing.sv", and the core file is correspondingly called
"ibex_core_tracing.core. The core in it is called
"lowrisc:ibex:ibex_core_tracing".
- Finally to keep symmetry, the toplevel of Ibex itself got renamed in
the core file from "lowrisc:ibex:ibex" to "lowrisc:ibex:ibex_core".
This ensures that we have the same name for the core file, the source
entry point, and the core name.
IMPORTANT NOTE:
If you apply this change and use fusesoc, you need to adjust the name of
the core dependency from "lowrisc:ibex:ibex" to
"lowrisc:ibex:ibex_core".
