* remove parameter BranchPredictor
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove references to the removed parameter(s) from examples
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from compliance verification
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from core lists
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from the example configurations
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove references to the removed parameter from documentation
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove related and dead code
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
---------
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove parameter option WritebackStage
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from examples
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from compliance verification
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from formal verification code generated for SymbioticEDA
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove reference to the deleted parameterd from the documentation
Do not refer to WriteBack as to a stage
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove related code to Writeback stage
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Removal of related and dead code after Writeback-stage removal
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* substitute ASSERT macro with one ignoring rst_ni and clk signals
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* keep clk_i and rst_ni for the sake of assert alone
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* BUGFIX: reintroduce en_wb signal between id and wb
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
---------
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove BranchTargetALU param.
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from the documentation
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from the example configurations
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from examples
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from compliance verification
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from core lists
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove references to the removed parameter(s) from Yosys framework configuration parser
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
---------
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
This is to allow more consistent signalling in systems that integrate
Ibex (e.g. OpenTitan) so bus integrity errors external to Ibex and one's
detected within Ibex can be fed into the same alert whilst seperating
out Ibex's various internal alert causes.
This commit includes switching to a scrambling RAM primitive for
ICache data and tag RAMs. Also introduces minor changes to ICache
to handle scrambling key valid signal.
It also includes a minor bug fix regarding not initializing
`fill_way_q` signal without ResetAll parameter. When the parameter
is not set and we have our first hit right after ICache enables,
the signal hangs.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.
Ibex testbench extended to generate the expected bits.
All other top-levels modified to add the new signals (which are mostly
ignored).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit adds power analysis scripts to the Arty A7
example design. They can be used by setting the newly
added `FPGAPowerAnalysis` parameter to 1.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
1-Port RAM is removed because of both execution and performance
issues. CLKIN1_PERIOD parameter is defined in clkgen module
for Vivado simulations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit updates link.ld RAM length to include max BRAM capacity
for Arty A7-35. It also changes coremark makefile to include a .vmem
output, which then can be used for FPGA implementations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This invocation would break:
make -C examples/sw/led/ CC=/opt/lowrisc-toolchain-gcc-rv32imc-20210412-1/bin/riscv32-unknown-elf-gcc
because the "-gcc" occurence inside the directory name would also be replaced.
Fix by first deriving CROSS_COMPILE from CC, then conditionally build other tool file names/paths.
Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.
There are no functional changes in this commit, only wiring.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
f29a0f7a7115e03fba734b1c00691c253aceb07e. The list of OpenTitan
changes that are merged in appears at the bottom of the commit.
There are some manual changes needed to adapt the code to work with
these changes.
- The ICache monitors need some extra types to adapt to the (rather
odd) data model that the OpenTitan dv_lib code now uses, where a
monitor needs to know an agent's associated sequence type.
- Verilator simulations now use MemArea slightly differently
OpenTitan changes:
* [dv] Allow monitor items to have different types from sequence items
(Rupert Swarbrick)
* [dvsim] Fix primary_cfg handling (Srikrishna Iyer)
* [dvsim] Deal with non unicode chars in log files (Srikrishna Iyer)
* [dvsim] Added common build fail patterns (Srikrishna Iyer)
* [dvsim] Minot cleanup to the lint flow (Srikrishna Iyer)
* [dvsim] Minor cleanups to to formal flow (Srikrishna Iyer)
* [dvsim] Fixes to UNR and cov analysis flows (Srikrishna Iyer)
* [dvsim] Very minor cleanup of Deploy class (Srikrishna Iyer)
* [dvsim] LsfLauncher report early errors as F (Srikrishna Iyer)
* [dvsim] Minor fix in clean_odirs function (Srikrishna Iyer)
* [chip dv] Set +sw_images as comma-separated list (Srikrishna Iyer)
* [flash_ctrl] Split tl intefaces for flash_ctrl and prim_flash_cfg
(Timothy Chen)
* [keymgr] Fix input value checks (Timothy Chen)
* [formal/script] Update generic formal flow naming from `fpv` to
`formal` (Cindy Chen)
* [top, prim] Address wmask and data width mismatch issue (Timothy
Chen)
* [dvsim] Add GUI mode for running simulations (Srikrishna Iyer)
* [dv] Fix reg backdoor (Weicai Yang)
* [dpi] Make an "ECC32" flavour of MemArea (Rupert Swarbrick)
* [uvmdvgen] Fix has_interrupts in env_cfg (Cindy Chen)
* [dvsim] Keep dependencies list (Srikrishna Iyer)
* [prim_prince] Reverse the k0||k1 mapping to match with the paper
(Michael Schaffner)
* [dvsim] Fix printing of last 10 lines (Srikrishna Iyer)
* [primgen] Minor fix to enable types with underscores (Michael
Schaffner)
* [dvsim] Prevent command echo suppression (Srikrishna Iyer)
* [dvsim] Spot fixes for LSF and internal launcher (Srikrishna Iyer)
* [sva] csr assertion dependency update (Cindy Chen)
* [memutil] Change DpiMemUtil so that it no longer owns MemAreas
(Rupert Swarbrick)
* [memutil] Factor out MemArea as a class (Rupert Swarbrick)
* [prim] Split out PRESENT and PRINCE support from prim:all (Rupert
Swarbrick)
* [fpv/otp_ctrl] Disable assertions due to lc_esc_en (Cindy Chen)
* [prim_prince] Annotate some arrays to avoid UNOPTFLAT warnings
(Rupert Swarbrick)
* [top] Hook up latest ast ports and complete a few other integration
(Timothy Chen)
* Eliminate `#pragma once` in favor of include guards (Chris Frantz)
* [sw,dv] Update headers to pass fix_include_guards.py (Alex Bradbury)
* [xbar/dv] Fix assertion error due to short reset (Weicai Yang)
* [sram] Add memory initialization (Timothy Chen)
* [uvmdvgen] Update links in checklist template (Philipp Wagner)
* [dv/uvmdvgen] Add comment for testplan (Cindy Chen)
* [dv/top_earlgrey] chip csr_aliasing timeout (Cindy Chen)
* [dvsim] Cosmetic updates to launcher methods (Srikrishna Iyer)
* [dv] Update csr_wr to support field write (Weicai Yang)
* [dv/common] Fix regression warnings (Cindy Chen)
* [dv] Get blocks with multiple device interfaces working with chip DV
(Rupert Swarbrick)
* [doc] Use relative links in Hjson-related shortcodes (Philipp
Wagner)
* [dvsim] minor enhancement to clean_odir (Srikrishna Iyer)
* [dvsim] Statically display jobs' status (Srikrishna Iyer)
* [dvsim] Do weighted scheduling of jobs (Srikrishna Iyer)
* [dvsim] Schedule jobs by dependency (Srikrishna Iyer)
* [dv] Xcelium UNR typo (Srikrishna Iyer)
* [dvsim] Implement LsfLauncher (Srikrishna Iyer)
* [dv/chip] solve same_csr_outstanding_timeout (Cindy Chen)
* [dv] make dv_base_agent work for high-level agent (Weicai Yang)
* [tools/dv] added UNR flow for xcelium (Rasmus Madsen)
* [prim] Split prim:subreg out of prim:all (Rupert Swarbrick)
* [prim] Split prim_alert_* out of prim:all (Rupert Swarbrick)
* [prim] Split out fifos into a prim_fifo core (Rupert Swarbrick)
* [prim] Split out arbiters into a prim_arbiter core (Rupert
Swarbrick)
* [prim] Make prim:flop_2sync depend on prim:flop (Rupert Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
Anyone who needs to disassemble their generated ELF can probably just
call objdump directly and the precise set of flags have already
confused at least one potential contributor[1].
We're keeping the canned objdump command for "engineers that know
where to look" because some have said they find it useful. Run it with
e.g.
make -C examples/sw/simple_system/hello_test disassemble
[1] https://github.com/lowRISC/ibex/issues/1263
The -Wwarn-IMPERFECTSCH flag is suggested in the Verilator docs (to
help spot if we get a clock gating hint wrong). The waiver is no
longer needed because we now add the relevant hint in the
RTL (vendored in prim_generic_clock_gating.sv from OpenTitan).
Previous lint fix was incorrect. The 'always_comb' block here should be
an 'always'. It is not combinational logic but rather an infinite loop
to generate a clock when running in a simulator that isn't verilator
(e.g. under simple-system under VCS) so the use of 'always' is
appropriate.
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
The documentation restructure in #1119 resulted in a new URL for the
documentation on Ibex system examples. This commit updates the in-tree
link to reference that new URL.
Signed-off-by: Alex Bradbury <asb@lowrisc.org>
Adding the "small" sections to the example linker script. This ensures
that all sections of memory needing to be zeroed are captured.
Fixes#1092
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
At some point in the future, the version of binutils we're using, and
the released version of LLVM, will coincide to use the correct name. In
the meantime, this change just uses the number which is supported by
both compilers.
This is, as I understand it, the only stumbling block to compiling the
in-repo C benchmark code with both GCC and LLVM. Being able to do so
would make it much easier for us to do comparisons on the benchmarks for
both compilers.
Signed-off-by: Sam Elliott <selliott@lowrisc.org>
This commit replaces the previous combination of `RV32M` bit parameter
used to en/disable the M extension and the `MultiplierImplementation`
used to select the multiplier implementation by a single enum parameter.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit makes sure that whenever Vivado is used, the Verilog
define `FPGA_XILINX` is set. This define can be used to enable Xilinx
specific pragmas in the RTL code. It is currently used to implement
the performance counters with DSP slices (incl. integrated output
registers for counter widths <= 32) which helps to save logic resources
and FFs (-7% and -15% when using e.g. 10 counters).
Previously, we had to set this parameter in every single top-level .core
file using Ibex.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- Add a major and minor alert output which can be used by the system to
react to fault injection attacks
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
