- Before this fix, the branch signal was qualified by the illegal
instruction signal and the illegal csr signal.
- This patch removes both of these since the decoder already masks
branches with illegal isntruction, and a branch cannot be a CSR op.
- This improves the worst path in the design significantly without the
branch target ALU.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Create separate operand muxes for the branch/jump target ALU
- Complete jump instructions in one cycle when BT ALU configured
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Use a toolchain in CI which has support for experimental bitmanip
patches. This toolchain is based on GCC 9.2.0 with additional bitmanip
patches, and reports itself as 10.0 experimental.
The toolchain was prepared by Luís Marques in
lowRISC/lowrisc-toolchains#11. Thanks!
Addresses part of #703
- valid_o could be asserted for one cycle then dropped when receiving
rvalid data for a request which has branched into the middle of a
line.
- This fix keeps valid_o asserted by using the offset version of
fill_rvd_cnt_q (fill_rvd_beat) to compare against fill_out_cnt_q
(which is also offset by the branch).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Speculative requests observing a PMP error shouldn't increment the
external request counter
- Remove redundant logic on fill_rvd_exp
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Add parameters and actual instantiation of icache
- Add a custom CSR in the M-mode custom RW range to enable the cache
- Wire up the cache invalidation signal to trigger on fence.i
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The option to limit the verilator simulation's maximum number of cycles was
implemented in terms of the `time_` variable, which counts half cycles. This
patch makes the limit respect the requested number of full cycles.
The patch divides `time_` by 2, instead of multiplying `term_after_cycles_`
by 2, as that better conveys the intended semantics, and slightly increases
the range of the limit. Related computations were modified for consistency.
mtval should record which half of the instruction caused the error
rather than just recording the PC.
An extra signal is added in the IF stage to indicate when an error is
caused by the second half of an unaligned instruction. This signal is
then used to increment the PC by 2 for mtval capture on an error.
Fixes#709
Instruction requests triggering PMP errors have their external request
suppressed. The beat counting logic therefore needs to know that these
requests will never receive any rvalid data responses.
This fix stops the external request counter from incrementing, and marks
all external requests complete as soon as any error is received.
The data in the cache line beyond the error is not required since the
core cannot access it without consuming the error first.
- Bring in a version of ram primitive with configurable width similar to
the OT RAM primitive.
- Change the RAM banking structure to be a single bank of LineSize (64
bits) to match the upcoming ECC granularity.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Run
```
fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_core
```
to format all source code with Verible's verilog_format tool.
This extends the core file to be able to call Verible for lint.
This requires an updated version of edalize with
https://github.com/olofk/edalize/issues/95 fixed. For the time being, we
use the same 'ot' branches of those tools as we do in OpenTitan. Once
Verible becomes officially supported we need to ensure that released
versions of fusesoc and edalize exist, and that this requirement is
properly documented.
The design currently relies on fill_done remaining set in the cycle
after the fill buffer completes to ensure the fill_older_q entry gets
cleared (when a fill buffer completes in the same cycle that one is
allocated). This fix makes the behaviour a bit more consistent and easy
to reason about.
When we run sim.py, we get commands to run the simulator from the YAML
file named by the --simulator_yaml argument, which defaults to
yaml/rtl_simulation.yaml.
This patch makes the argument explicit in the Makefile and adds a
dependency on that file for commands that read it.
This fixes a bug mentioned in issue #674, where dumped wave files were
ending up in dv/uvm/core_ibex, rather than a test-specific output
directory.
It turns out that this is because of my change in commit 08fc2a4,
which runs the simulator in the top core_ibex directory, rather than
changing directories each time. We have to do this to make the
parallel LSF flow work (which presumably has never actually been run,
otherwise we'd have noticed it was broken).
There are two ways I can think of getting this to work. Probably the
cleanest approach is to generate a script for each test, which looks
something like "cd test_dir; setup_stuff; run_simulator". This would
work (and is how I've seen it done in the past), but doesn't really
fit in with the string interpolation/YAML stuff we've got here.
Instead, this patch goes for a hackier approach, where we prefix the
simulation command with "env SIM_DIR=<out>" and then use the SIM_DIR
environment variable in the TCL scripts to figure out where to put the
wave file. This is kind of icky long-term, but should work for now.
I've also got rid of the code that appends some extra plusargs and a
log argument to the simulation command; now, the relevant variables
get substituted in and the actual command is found in
rtl_simulation.yaml.
For packed structs used as input/output port, Questa reports
"Defaulting port 'irqs_i' kind to 'var' rather than 'wire'
due to default compile option setting of -svinputport=relaxed."
The relevant help message says:
```
verror 13314:
vlog Message # 13314:
An input port that is declared with a type but without the 'var' keyword
should default to 'wire' for strict LRM conformance. The default compile
option of -svinputport=relaxed is not LRM compliant, and only defaults
4-state scalar or 4-state single dimension vector types to 'wire'.
Consider using -svinputport=net for strict conformance. See the vlog -help
text for other behaviors available with the -svinputport option.
```
In our code base we can rely on the LRM-compliant handling of this
construct and opt into that using `-svinputport=net`.
Fixes#670
Assert macros in prim_assert.sv report the asserted property as part of
the error message if the assertion fails. Doing that requires us to
stringify the property. If the property is multi-line in the source
code, this produces a multi-line string. According to the
SystemVerilog standard, a multi-line string requires a backslash (`\`)
at the end of a line. Adding this backslash through a macro is not
possible (at least to my knowledge), giving us no way to produce a
standards-compliant implementation of the `ASSERT` macros that report
the property as string.
This commit therefore removes the property from the error message if an
assertion fails. It makes these messages less useful, but the
information can still be recovered in a less convenient way through the
name of the assertion, and the file and line numbers. File and line
number were missing from the non-UVM code path before, this commit adds
them there as well.
Fixes#669
Verible doesn't do real pre-processing currently, and fails to parse
code if define sections span across headers of blocks, as we did.
Use another syntax instead for the one case where we did that to work
around this limitation. The code isn't less readable as result, making
this an acceptable trade-off.
Works around https://github.com/google/verible/issues/228
syn/ filling up with result directories is a little annoying, this sets
up the default so everything ends up generated under syn/syn_out/. Flow
users can easily change this to meet their personal requirements.
- ready_i input to the prefetch buffer factored both it's own valid_o
output and the pc_set branch signal, neither of which are required.
- Refactoring the ready_i signal to just id_in_ready_i improves timing
significantly for the icache.
- Also removed offset_in_init signal which appeared to serve no purpose.
This adds a dependency on $(TESTLIST) (which is that file) for each
target that depends on $(TEST_OPTS), a set of command line options
that includes --testlist=$(TESTLIST).
In practice, we could actually just add the dependency to the
$(metadata)/instr_gen.gen.stamp target, since all the other affected
targets transitively depend on that, but this seems a little confusing
so I've made the dependency explicit.
This is mostly just adding comments and docstrings and pulling the
guts of the comparison into its own function.
I've also got rid of the subprocess calls for appending to a log file
and now calculate the pass/fail count from the return codes of the
checkers rather than grepping in the regression log (hopefully it
gives the same result!)
