The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Andreas Traber 03a43245c7 Oops, fetch_addr_Q was multiply driven		2015-09-02 10:27:52 +02:00
include	Add support to debug unit to set the Program Counter	2015-09-01 18:18:02 +02:00
.gitignore	Added vim swap file	2015-07-24 15:26:32 +02:00
alu.sv	Use 'x to simplify synthesis	2015-09-02 09:25:06 +02:00
compressed_decoder.sv	Use 'x to simplify synthesis	2015-09-02 09:25:06 +02:00
controller.sv	Add support to debug unit to set the Program Counter	2015-09-01 18:18:02 +02:00
cs_registers.sv	Fix width of irq_enable signal	2015-09-02 09:30:03 +02:00
debug_unit.sv	Rework pipeline flushes and exceptions	2015-08-31 10:02:55 +02:00
ex_stage.sv	Move LSU related signals out of ex_stage and alu and put them inside LSU	2015-09-02 08:55:44 +02:00
exc_controller.sv	Readd ALU flag to EX stage, use it for branch decision	2015-08-31 13:06:43 +02:00
hwloop_controller.sv	Cosmetic changes in hwloop controller, ID and includes	2015-08-31 12:34:33 +02:00
hwloop_regs.sv	Fix hwloop code indentation	2015-08-31 12:33:27 +02:00
id_stage.sv	New CSR implementation, fix irq_enable signal	2015-09-02 01:39:07 +02:00
if_stage.sv	Oops, fetch_addr_Q was multiply driven	2015-09-02 10:27:52 +02:00
instr_core_interface.sv	Oops, fetch_addr_Q was multiply driven	2015-09-02 10:27:52 +02:00
load_store_unit.sv	Move LSU related signals out of ex_stage and alu and put them inside LSU	2015-09-02 08:55:44 +02:00
mult.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
register_file.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
riscv_core.sv	Move LSU related signals out of ex_stage and alu and put them inside LSU	2015-09-02 08:55:44 +02:00