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1676 commits

Author SHA1 Message Date
Ross Thompson
cc58bfdcf3 Removed more *** from the ifu. 2024-06-19 09:49:17 -07:00
Ross Thompson
ab1ee3d69b Removed *** from IFU, lrcs. 2024-06-19 09:40:35 -07:00
Ross Thompson
ab1af0fabf Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2024-06-19 09:25:39 -07:00
David Harris
10e6d5846b Removed unnecessary Umfirst from early termination 2024-06-19 09:18:51 -07:00
David Harris
4b4980e42d Fixed undriven OutFmt 2024-06-19 09:17:32 -07:00
David Harris
54cb612577 Fixed lint error in fdivsqrtpreproc for rv32 IDIV_ON_FPU 2024-06-19 07:48:54 -07:00
Ross Thompson
2581ea0b74 Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames. 2024-06-18 16:48:49 -07:00
David Harris
301ded05f8 Unused signal cleanup 2024-06-18 08:15:48 -07:00
David Harris
cb563e8018 Clean up unused signals 2024-06-18 08:07:14 -07:00
Ross Thompson
00e0549c36 I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word. 
The default input interface to the interface is 8-bit and I used 32-bit.  I suspect there is a bug in the implementation for non-8-bit interfaces.
 2024-06-18 07:44:19 -07:00
David Harris
c1fd7a9589 Removed unused signals 2024-06-18 07:28:52 -07:00
David Harris
8bae52b09d Lint cleanup of unused signals 2024-06-18 06:49:17 -07:00
David Harris
45f505250c Lint cleanup 2024-06-18 06:23:43 -07:00
David Harris
3fa37b0233 Lint cleanup 2024-06-18 06:15:17 -07:00
David Harris
cac67aae4f Lint cleanup 2024-06-18 05:58:54 -07:00
David Harris
ecae1100f6 Lint cleanup 2024-06-18 05:49:49 -07:00
David Harris
7509e856df Removed asynchronous reset causing lint issue in peripherals 2024-06-18 05:49:12 -07:00
David Harris
2fc9edff45 Fixed Issue #752 of Verilator simulation by changing LRUMemory to be nonblocking now that Verilator handles this construct properly 2024-06-18 04:40:38 -07:00
Ross Thompson
cccb40e4b5 Got the tracer not overrunning ethernet buffers so frames are not being dropped. 2024-06-17 09:16:24 -07:00
David Harris
4a4bbdfc43 More code cleanup 2024-06-14 09:50:07 -07:00
David Harris
53477b2c85 Code cleanup 2024-06-14 07:08:17 -07:00
David Harris
8f09240e6c Simplified outdated documentation pointers 2024-06-14 03:42:15 -07:00
David Harris
b1c9450b4a Code cleanup: RAM, fdivsqrt 2024-06-14 03:35:05 -07:00
David Harris
6789f32154 Starting code cleanup 2024-06-14 02:54:43 -07:00
Ross Thompson
47523c97ac Getting closer to figuring out the lost ethernet frame bugs. 2024-06-13 15:46:54 -07:00
Rose Thompson
b77fcd70e6 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-06-13 13:58:07 -05:00
David Harris
28142eff64 Formatting shiftcorrection 2024-06-12 04:25:13 -07:00
David Harris
b7e2f34966 shiftcorrection cleanup 2024-06-12 03:59:55 -07:00
Ross Thompson
563980443a Merge branch 'main' into rvvi 2024-06-10 18:10:23 -07:00
David Harris
e02c1008bc postprocessor shift amount simplification 2024-06-10 07:55:35 -07:00
David Harris
3284dd2112 Removed unnecessary Zero checking on FmaPreResultSubnorm 2024-06-10 07:45:03 -07:00
David Harris
4c066c078f Removing two unnecessary 0's from fmashiftcalc interface 2024-06-10 07:38:03 -07:00
David Harris
1873064be5 Simplified fround exact case 2024-06-10 06:23:42 -07:00
David Harris
5094122048 Simplifying fround 2024-06-10 06:11:55 -07:00
David Harris
8b887755c9 Simplified 3:1 mux to 2:1 mux when only Zbkc is supported and clmulr is not needed 2024-06-10 02:34:35 -07:00
Rose Thompson
5dfde808f0
Merge pull request #827 from davidharrishmc/dev 
Fixed support for individual crypto extensions without Zb*
 2024-06-06 09:31:07 -05:00
David Harris
9489771bd7 Fixed support for individual crypto extensions without Zb* 2024-06-05 22:57:39 -07:00
Rose Thompson
fc62f80407 Closer to fully working hardware tracer. 2024-06-04 11:31:05 -05:00
Rose Thompson
80f98b3223 now have a working ethernet daemon to collect frames and partially decode into RVVI. 2024-06-04 10:20:51 -05:00
Rose Thompson
dc904cdbbb The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field. 2024-06-03 18:10:25 -05:00
Rose Thompson
0ca10e7ee2 Last of the branch predictor signal name updates. 2024-06-02 17:01:51 -05:00
Rose Thompson
04744032d8 Updated more signal names to match book. 2024-06-02 16:59:11 -05:00
Rose Thompson
b45b7ff7d6 Signal name changes to match book. 2024-06-02 16:32:25 -05:00
Rose Thompson
731e1fe08f Updated spill logic to reflect changes in textbook. 2024-06-02 15:48:42 -05:00
Rose Thompson
a830bd57f0 Have to reverse the byte order for ethernet frame length. 2024-05-31 17:46:43 -05:00
Rose Thompson
e05ebc30b8 Almost worked out the bugs in packetizer. 2024-05-31 16:48:41 -05:00
Rose Thompson
0dccc6051d draft of receiving code to unpack the ethernet frames into rvvi. 2024-05-31 13:55:25 -05:00
Rose Thompson
1df3e5239a This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer. 
wireshark is able to capture the frames and they match the expected data!
 2024-05-30 17:57:28 -05:00
Rose Thompson
ca90c6ba48 Added the ethernet files. These are part of another repo. 
We should remove before mainlining this.
 2024-05-30 16:33:49 -05:00
Rose Thompson
9703055758 The FPGA is synthesizing with the rvvi and ethernet hardware. 2024-05-30 15:37:17 -05:00