github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-19 03:24:50 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
11051 commits 7 branches 2 tags 54 MiB
Commit graph

1676 commits

Author SHA1 Message Date
David Harris
9a46061716 100% coverage tlbcontrol 2025-04-18 19:15:07 -07:00
David Harris
ae2846b1ec Cleaned up HPTW reset 2025-04-17 11:22:17 -07:00
David Harris
42f78c645b
Merge pull request #1363 from coreyqh/ccov 
Full privdec code coverage
 2025-04-15 12:33:16 -07:00
Corey Hickson
91e919395b CSRC full coverage 2025-04-15 11:07:55 -07:00
David Harris
eb88a9e85e Use effective privilege mode in PMP checking 2025-04-13 04:42:35 -07:00
David Harris
a1000c19ea Checking PMP TOR bound against length of access to fix Wally against the riscv-arch-test pmp64-TOR* tests. Still has known limitation in issue #1354, but passes tests, which are now reenabled 2025-04-12 19:36:59 -07:00
David Harris
521344b8b5 Fixed mstatus bits that should be read-only zero in certain configs (issue #1315) 2025-04-11 16:57:41 -07:00
David Harris
0528337a4a SUM and SPP are write only zeros if SATP and S are not supported 2025-04-11 16:21:05 -07:00
David Harris
3809b292c1 Decompressed and mmu coverage fixes 2025-04-11 06:42:20 -07:00
David Harris
2ad4f20900
Merge pull request #1351 from coreyqh/ccov
Some checks failed
Lint / Lint (Python 312) (push) Has been cancelled
Details
Lint / Lint (Python 39) (push) Has been cancelled
Details 
Full csru code coverage
 2025-04-09 11:05:35 -07:00
Corey Hickson
683c0cac86 Comment explaining redundant mstatus.FS check 2025-04-09 11:04:30 -07:00
David Harris
ade5b2225a
Merge pull request #1344 from coreyqh/ccov 
Align and FPU code coverage
 2025-04-09 01:27:59 -07:00
Jordan Carlin
204b3d303a
Merge pull request #1347 from davidharrishmc/dev
Some checks are pending
Lint / Python 312 lint (push) Waiting to run
Details
Lint / Python 39 lint (push) Waiting to run
Details 
Fixed cvw-arch-verif Issue #553 about misaligned lr/sc needs to throw…
 2025-04-08 16:40:25 -07:00
David Harris
e9ea1f59c4 Fixed cvw-arch-verif Issue #553 about misaligned lr/sc needs to throw access fault 2025-04-08 16:38:26 -07:00
Corey Hickson
7375635110 Full align code coverage 2025-04-08 01:51:22 -07:00
Corey Hickson
b86026abbe Fixed FlushD exclusion 2025-04-03 10:16:54 -07:00
Corey Hickson
a9ec44746e Change LatestUnstalledD exclusion to only impossible scenarios 2025-04-02 23:50:34 -07:00
Corey Hickson
cc8a5b152f exclude only impossible scenarios rather than whole line 2025-04-02 18:06:19 -07:00
Corey Hickson
e6b3b3cec5 Code coverage exclusions for signals related to StallFCause 2025-04-02 02:07:58 -07:00
Corey Hickson
64a741c0b7 Restored previous RTL with coverage exclusion 2025-04-02 02:06:46 -07:00
Corey Hickson
0995c85452 Merge branch 'main' of https://github.com/openhwgroup/cvw into ccov 2025-04-02 00:29:24 -07:00
Jordan Carlin
4b7be3e1ea
Fix mstatus.MPP write logic 2025-03-19 15:50:59 -07:00
Jordan Carlin
6e8759cc96
Trap on illegal instructions when no FPU 2025-03-19 14:50:14 -07:00
Corey Hickson
a799c8bdd9 100% fctrl code coverage 2025-03-13 04:52:24 -07:00
David Harris
18e6e65a33 Clean up synthesis warnings about signed conversion 2025-03-05 09:49:21 -08:00
David Harris
ad2bac0236 Clean up or suppress synthesis warnings 2025-03-05 08:46:54 -08:00
David Harris
a166b522e5 Fixed clock edge for Design Compiler compatibility 2025-03-05 08:39:25 -08:00
David Harris
96c3e93d5e Fixed typos in controller 2025-02-26 09:58:47 -08:00
Rose Thompson
fe7b5820ea Non-zero DAU bits in non-leaf PTE now cause page faults. 2025-02-25 14:54:59 -06:00
David Harris
c40450cc3a Fixed size bug and cleaned up PMP csr logic 2024-12-30 22:22:29 -08:00
David Harris
55b63ff486 Fixed PMP checking that top of access is still within range 2024-12-30 22:05:01 -08:00
David Harris
029f9e2d55 Fixed PMPCFG bits 6:5 need to be WARL 00 2024-12-30 19:16:59 -08:00
David Harris
c17b0c7d45 Improved naming of signals in TLB 2024-12-24 05:36:20 -08:00
Zain2050
7d57d83224 made changes for ResEnc in tlbcontrol 2024-12-24 01:38:03 -08:00
David Harris
45d4bf0f60 Typo fix 2024-12-23 06:22:11 -08:00
Rose Thompson
d31622fa21
Merge pull request #1103 from JacobPease/main 
Made minor changes to the controller to clean up the logic. Still need to simplify the first always block.
 2024-12-03 17:03:43 -06:00
David Harris
155d1d511b Fixed funct7 code for sinval.vma (issue #1154) 2024-11-29 11:39:24 -08:00
David Harris
58bfc27c63 Fixed decoder for illegal 0b1e0c33 issue #1152 2024-11-29 11:20:12 -08:00
David Harris
cf47dd7e6b Fixed bmu shift decode logic: bad funct7 for variable shifts, commented better, removed unnecessary guard 2024-11-29 05:58:14 -08:00
David Harris
722dc9bfda Throw illegal instruction for RV64 W-type shifts with amounts > 31 2024-11-28 16:34:43 -08:00
David Harris
3f6611dd3a Fixed fmv.d.x / fmv.x.d only on RV64 2024-11-28 14:47:58 -08:00
David Harris
f1072e46e1 fcvt to/fron long only allowed in RV64 2024-11-28 14:40:09 -08:00
David Harris
9116ffa45d Fixed Issue #1147 that w-type shifts do not throw illegal instruction trap in RV32GC 2024-11-28 13:36:31 -08:00
David Harris
37c6879805 Fixed decoder bug that doesn't throw illegal instruction exception for RV32 immediate shifts by more than 31 2024-11-27 15:12:11 -08:00
Rose Thompson
2f04e5e597 Merge branch 'main' of github.com:rosethompson/cvw 2024-11-25 15:53:27 -06:00
Rose Thompson
7358c1fe67 Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status. 2024-11-25 15:50:29 -06:00
David Harris
ce7b036b78
Merge pull request #1109 from jordancarlin/lint 
More lint cleanup: remove unused params
 2024-11-16 16:34:15 -08:00
Jacob Pease
2dcfe10013 Merged changes and reverted my commits. 2024-11-16 14:50:06 -06:00
Jordan Carlin
f6b0805fd4
More lint cleanup: remove unused params 2024-11-16 12:35:37 -08:00
Jacob Pease
dda3cd6bea Removed unnecessary separate if statement. 2024-11-16 14:29:58 -06:00