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1698 commits

Author SHA1 Message Date
David Harris
d7c30f5f1f Fixed bug decoding svinval instructions and checking TVM 2025-06-05 16:54:15 -07:00
David Harris
c8da70738e Fixing comments from Jordan 2025-06-04 10:42:40 -07:00
David Harris
e013c57b9b Removed TooBig logic and PMP Top checking now that grain size is set to prevent accesses that wrap a region 2025-06-01 06:48:18 -07:00
David Harris
874d8d2efd Removed unused line 2025-06-01 05:27:12 -07:00
David Harris
11ff08d0ac PMP granularity support 2025-05-27 03:59:26 -07:00
David Harris
638cda23b4 Cleanup 2025-05-27 03:34:14 -07:00
David Harris
0fabccf384 Fixed simulation issues in trickbox 2025-05-21 12:12:54 -07:00
David Harris
9dc82f38fc Initial trickbox 2025-05-21 10:26:32 -07:00
David Harris
e3ae285a8e Resolved pmpaddrdec merge 2025-05-08 15:07:52 -07:00
Rose Thompson
b311717385 Merge branch 'main' of github.com:rosethompson/cvw 2025-05-08 13:23:44 -05:00
Rose Thompson
8b35d72122 EBU simplifications. 2025-05-08 13:23:31 -05:00
Rose Thompson
8369e8679e
Merge branch 'openhwgroup:main' into main 2025-05-08 13:21:33 -05:00
Rose Thompson
17cd5cddaa A little cheaper implementation. Uses 3 extra 1 bit registers, 1 XLEN-bit incrementer, and 1 XLEN-mux, rather than 3 XLEN registers. 2025-05-08 13:19:26 -05:00
David Harris
bed00c80d2
Merge pull request #1409 from jordancarlin/spelling 
Fix lots of spelling errors
 2025-05-08 04:58:11 -07:00
Jordan Carlin
5271234591
Fix lots of spelling errors 2025-05-08 00:18:38 -07:00
Rose Thompson
03653f0336 Fixed the xtval misaligned address issue. 2025-05-07 16:26:05 -05:00
Rose Thompson
950cdba298 Fixed align module so that spilled addresses are aligned to native word type rather than + cacheline in bytes over the effective address. This ensures xtval is set to the aligned byte for the second half of the access. 2025-05-07 14:00:07 -05:00
Rose Thompson
52c5e515b7 Second fix for the zsh bug. Fixes issue #1263. A misaligned load or store page fault generates two virtual memory address translations. If the second page faults, xtval should be updated with the address of the second part of the instruction not the first part. 2025-05-06 19:24:05 -05:00
Rose Thompson
3969933327 Possible solution to the misaligned virtual page bug. 2025-05-05 18:53:33 -05:00
David Harris
18a7a231ce Initial pmpadrdec grain implementation 2025-05-05 16:20:44 -07:00
David Harris
90b4337a49 Support PMP granularity G > 0 in PMP registers 2025-05-05 15:29:30 -07:00
David Harris
97f5ea0fd1 Defined PMP_G granularity parameter 2025-05-05 11:46:37 -07:00
David Harris
9a46061716 100% coverage tlbcontrol 2025-04-18 19:15:07 -07:00
David Harris
ae2846b1ec Cleaned up HPTW reset 2025-04-17 11:22:17 -07:00
David Harris
42f78c645b
Merge pull request #1363 from coreyqh/ccov 
Full privdec code coverage
 2025-04-15 12:33:16 -07:00
Corey Hickson
91e919395b CSRC full coverage 2025-04-15 11:07:55 -07:00
David Harris
eb88a9e85e Use effective privilege mode in PMP checking 2025-04-13 04:42:35 -07:00
David Harris
a1000c19ea Checking PMP TOR bound against length of access to fix Wally against the riscv-arch-test pmp64-TOR* tests. Still has known limitation in issue #1354, but passes tests, which are now reenabled 2025-04-12 19:36:59 -07:00
David Harris
521344b8b5 Fixed mstatus bits that should be read-only zero in certain configs (issue #1315) 2025-04-11 16:57:41 -07:00
David Harris
0528337a4a SUM and SPP are write only zeros if SATP and S are not supported 2025-04-11 16:21:05 -07:00
David Harris
3809b292c1 Decompressed and mmu coverage fixes 2025-04-11 06:42:20 -07:00
David Harris
2ad4f20900
Merge pull request #1351 from coreyqh/ccov
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Full csru code coverage
 2025-04-09 11:05:35 -07:00
Corey Hickson
683c0cac86 Comment explaining redundant mstatus.FS check 2025-04-09 11:04:30 -07:00
David Harris
ade5b2225a
Merge pull request #1344 from coreyqh/ccov 
Align and FPU code coverage
 2025-04-09 01:27:59 -07:00
Jordan Carlin
204b3d303a
Merge pull request #1347 from davidharrishmc/dev
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Fixed cvw-arch-verif Issue #553 about misaligned lr/sc needs to throw…
 2025-04-08 16:40:25 -07:00
David Harris
e9ea1f59c4 Fixed cvw-arch-verif Issue #553 about misaligned lr/sc needs to throw access fault 2025-04-08 16:38:26 -07:00
Corey Hickson
7375635110 Full align code coverage 2025-04-08 01:51:22 -07:00
Corey Hickson
b86026abbe Fixed FlushD exclusion 2025-04-03 10:16:54 -07:00
Corey Hickson
a9ec44746e Change LatestUnstalledD exclusion to only impossible scenarios 2025-04-02 23:50:34 -07:00
Corey Hickson
cc8a5b152f exclude only impossible scenarios rather than whole line 2025-04-02 18:06:19 -07:00
Corey Hickson
e6b3b3cec5 Code coverage exclusions for signals related to StallFCause 2025-04-02 02:07:58 -07:00
Corey Hickson
64a741c0b7 Restored previous RTL with coverage exclusion 2025-04-02 02:06:46 -07:00
Corey Hickson
0995c85452 Merge branch 'main' of https://github.com/openhwgroup/cvw into ccov 2025-04-02 00:29:24 -07:00
Jordan Carlin
4b7be3e1ea
Fix mstatus.MPP write logic 2025-03-19 15:50:59 -07:00
Jordan Carlin
6e8759cc96
Trap on illegal instructions when no FPU 2025-03-19 14:50:14 -07:00
Corey Hickson
a799c8bdd9 100% fctrl code coverage 2025-03-13 04:52:24 -07:00
David Harris
18e6e65a33 Clean up synthesis warnings about signed conversion 2025-03-05 09:49:21 -08:00
David Harris
ad2bac0236 Clean up or suppress synthesis warnings 2025-03-05 08:46:54 -08:00
David Harris
a166b522e5 Fixed clock edge for Design Compiler compatibility 2025-03-05 08:39:25 -08:00
David Harris
96c3e93d5e Fixed typos in controller 2025-02-26 09:58:47 -08:00