Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.
Ibex testbench extended to generate the expected bits.
All other top-levels modified to add the new signals (which are mostly
ignored).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Previously the raw incremented address was used which is the calculated
address + 4. This is confusing as it refers to a byte that wouldn't be
accessed (e.g. a lw at 0x8000009e which faults on the access to
0x8000000a0, would report an mtval of 0x8000000a2). With this change
mtval will refer to the first byte on the other half of the word
boundary the unaligned access crosses.
Random constants are sent through the hierarchy as parameters in-line
with other OpenTitan modules.
Further detail on this mechanism can be found in lowrisc/opentitan#2229
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
mseccfg and mseccfgh have changed their addresses. This updates to the
newly allocated values.
The ePMP specification is now available as a versioned PDF,
documentation is updated to point to that removing the local PDF copy.
This commit adds power analysis scripts to the Arty A7
example design. They can be used by setting the newly
added `FPGAPowerAnalysis` parameter to 1.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
1-Port RAM is removed because of both execution and performance
issues. CLKIN1_PERIOD parameter is defined in clkgen module
for Vivado simulations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit updates link.ld RAM length to include max BRAM capacity
for Arty A7-35. It also changes coremark makefile to include a .vmem
output, which then can be used for FPGA implementations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
A minor change to use the Width parameter of prim_buf. No functional
impact but stops the hierarchy from being cluttered with hundreds of
generate contexts in the top level.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This parameter forces a reset of all registers inside the core. This is
required to guarantee a common starting point for lockstep and thus
prevent spurious lockstep failure alerts.
Another minor change in this commit rearranges the writeback stage
multiplexing to gate incoming lsu write data when not valid. This stops
any X values from the data bus propagating to the register file
signalling (and thus to the lockstep comparison) which would cause the
lockstep alert to be X. It has the side effect of possibly reducing
power consumption in the register file.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This invocation would break:
make -C examples/sw/led/ CC=/opt/lowrisc-toolchain-gcc-rv32imc-20210412-1/bin/riscv32-unknown-elf-gcc
because the "-gcc" occurence inside the directory name would also be replaced.
Fix by first deriving CROSS_COMPILE from CC, then conditionally build other tool file names/paths.
Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
We're already redirecting stdout to sim.log in run_rtl.py. Specifying
'-l' as well meant that VCS opened sim.log in a separate FD.
Suprisingly enough, this mostly worked, but not always! Just write
once :-)
This commits adds a yaml based intermediate format for test results.
compare.py serialises a TestRunResult (a named tuple type) into this
format for each test run it checks. collect_results.py reads them all
back in to produce reports.
Three reports are output:
- regr.log - plain text report much like the one previously produced
- regr_junit.xml, regr_junit_merged.xml - JUnit report format, the
_merged version batches together multiple tests to appear to be a
single test case under a test suite. This gives better results with
Azure's JUnit reporting.
This signal used to be a one shot enable out of reset. We need an option
to pause execution for OpenTitan, so fetch_enable is extended to cover
that.
The signal is already driven low by the testbench at the end of test.
This is moved after the performance counter reads to ensure they can
complete.
Fixes#1105
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Fix the reset polarity in the irq driver (clears irq signals to zero
on reset rather than them being x) plus remove an unused signal.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The test loops around waiting for the core to sleep then sending
interrupts to wake it. In some cases, the sequence sends an interrupt
that isn't enabled. It never gets back to try again with a new interrupt
since the test is waiting to see wfi first. This change removes that
requirement since it is redundant anyway (have to see wfi to sleep).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Commit 700f29b changed things so that details of the various tests
that ran ended up in separate files. This is nice (and important for
running things in parallel), but isn't massively helpful if you use
regr.log to understand what happened from a CI run!
This patch adds the logs again, splitting them up so that failing
tests come before passing ones (since you usually just care about the
failures).
This allows run.py to pass ISA options through to Spike. This relates to
the failure in #1369 (test inserts a bitmanip instruction which Spike
interprets as valid but the core treats as invalid depending on config).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The CSR tests don't currently support multiple configurations
(see #1333). Since the OpenTitan configuration is the only one currently
being run, update this file to pass with that for now.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
With data-independent timing enabled and BranchTargetALU configured,
branches will stall for a cycle causing an illegal value to be decoded
for the B Operand. No functional impact of this, but an assertion fires
so we might as well tie it off properly.
Fixes#1367
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
In tests with multiple resets, these signals could hold onto spurious
values through reset (since the clock is also gated) which caused
assertion failures on resumption.
Fixes#1368
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This patch teaches Make which tests we're actually running (via the
list_tests.py script), which means that we can compare the ISS and RTL
results in parallel rather than serially.
There's a bit of duplicated code (both list_tests.py and sim.py
currently contain the code to get a list of tests and then filter by
Ibex configuration), but this should go away with a later patch that
runs the RTL simulations in parallel in a similar way.
Note: This might seem a little silly: trace comparison takes way less
time than the RTL simulation! The point is that it's probably easier
to work "from the bottom" than to start by parallelising the
simulations themselves.
This makes path calculations a bit easier when it comes to loading
stuff up for comparison (allowing us to move more into the Makefile).
Long-term, it might also allow us to change how we track things
entirely, getting rid of the start-seed part of the output directory
structure.
The prim_buf.sv file in Ibex is a manual copy of a file which is
typically auto-generated by FuseSoC/primgen. However, Ibex DV doesn't
yet run FuseSoC, and we provide a pregenerated copy instead. The
auto-generated file and its copy got out of sync. Fix that by adding the
new Width parameter.
These changes match newer versions of Riviera. They work for all
versions >= 2020.04. Ibex itself only compiles successfully with
version 2021.04, so there's no need to maintain command-line
compatibility with older versions.
This adds the configuration instantiated in Opentitan and adds
missing prim support to allow the TB to run that configuration.
Resolves#1362
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
