Certain synthesis tools like DC are very smart at optimizing away redundant logic.
Hence, we have to insert an optimization barrier at the IOs of the lockstep Ibex.
This is achieved by manually buffering each bit using prim_buf.
Our Xilinx and DC synthesis flows make sure that these buffers cannot be optimized
away using keep attributes (Vivado) and size_only constraints (DC).
Signed-off-by: Michael Schaffner <msf@google.com>
1. Missing prim_assert in ibex_top.sv (more of an rtl bug but only found
in running synthesis scripts)
2. Write out the pre-mapped netlist before mapping latches
Relates to #1335
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This adds more instruction categories and corrects various issues in the
categorization code. Further cross coverage has been added including
illegal bins to remove bins that cannot occur.
The concept of using SVAs with cross coverage has been dropped. The
systemverilog scheduling model makes the concept unworkable.
The read enables should only be asserted where an actual RF read will
occur. Where there is an illegal instruction or a fetch error the raw
decoder signals might still be asserted but should be squashed before
they become the true enable signals.
csr_op_en_i signals whether or not the CSR access will actually happen,
but whether an illegal write is being can be determined with just the
address and access type. This change will improve timing and avoid
circular logic that might occur from the use of the illegal_csr_write
signal.
Note that the alert output is tied off for now until an option is added
to reset all registers (otherwise there will be X propagation).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.
There are no functional changes in this commit, only wiring.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
No functional change. These parameters are effectively fixed. Moving
them to the pkg eases top-level wiring of RAM signals.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This signal is used to gate several assertions related to
unknown/invalid selector signals. We want to be sure to catch any X
values entering the compressed decoder and ultimately ID.
This is related to lowRISC/Ibex#540.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This change will cause the ID stage to stall if there is a potential
debug mode entry until instructions in both ID and WB have completed.
This fixes an issue with incorrect behaviour around hardware breakpoints
and exceptions that could cause exception entry to be missed, hardware
breakpoints to be triggered incorrectly or missed entirely.
In addition single step control logic is altered to work correctly with
the new debug mode entry behaviour.
Changes the ECC granularity in the data RAMs from 64bit to 32bit. This
is to align with an upcoming change in bus ECC. Relates to
lowRISC/opentitan#5450
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit adds the MCOUNTEREN CSR as required by the RISC-V spec.
The register is defined as WARL. At the moment, Ibex doesn't enable U-mode
access to the performance montiors. Consequently, writes to the register are
ignored and it reads as zero which is okay according to the spec.
This resolveslowRISC/Ibex#1278 .
Prior to this change Ibex had multiple feedthrough paths from the data
memory interface to the instruction memory interface. This existed
because Ibex would hold off doing a instruction fetch for a jump or
branch if there was a outstanding memory request. It would wait for the
response to be available so either the jump or branch would occur or an
exception was taken.
With this change the branch or jump will speculatively begin the
instruction fetch whilst there is an outstanding memory request. Should
an exception result from the memory request the fetch will be discarded
and the exception taken as normal.
An alternative fix would not factor the data error response
(data_err_i) directly into the controller logic for branches and jumps.
With this option new stall cycles would be introduced anywhere a branch
or jump immediately follows a memory instruction which would have an
adverse impact on performance.
* `if` in `DBG_TAKEN_IF` is needless as the conditions it checks will be
true if controller enters `DBG_TAKEN_IF` state
* flop `enter_debug_mode` so `FLUSH` state looks at what
`enter_debug_mode` was when it was seen in `DECODE` state rather than
what it has become. In particular the controller could enter `FLUSH`
on the basis of performing a WFI then divert down the debug control
path due to a new debug request being raised. In this instance it is
preferable for the WFI to complete entering `SLEEP` before the debug
request wakes the core back up.
This implemements the RISC-V Trusted Execution Environment (TEE) working
group proposal 'PMP Enhancements for memory access and execution
prevention on Machine mode'. The proposal is awaiting ratification and
is not expected to change beyond minor tweaks before it becomes part of
the RISC-V priviledged specification.
No seperate 'classic' PMP only mode is provided as different PMP
behaviour only occurs when the MSECCFG CSR is written to. This CSR is
introduced by the proposal and has no specified function in the current
RISC-V priviledged specification.
The previous change was wrong: it was trying to define a signal with
DbgHwNumLen bits that contained DbgHwBreakNum - 1. Unfortunately, '1
is *not* the same as a zero-extended version of 1'b1.
DbgHwBreakNum - 1 is an int, so generates a warning if it's assigned
to tselect_d (of type logic [DbgHwNumLen-1:0]). Explicitly generate
the value we need as a localparam.
This lint warning doesn't appear by default in the Ibex repository,
because DbgTriggerEn is disabled. It does, however, appear in
OpenTitan because we enable it there.
This commit modifies the encoding of SROI, RORI, SBEXTI, GREVI and GORCI by
forcing Bit 26 to zero to prevent overlapping encodings with FSRI.
The bitmanip draft spec doesn't explicitly state that Bit 26 for those
instructions must be zero. However, those instructions only ever use
log2(XLEN) LSBs of the immediate. This means they don't use Bit 26 in RV32.
Instead, whenever Bit 26 is set, these instructions are instead decoded as
FSRI.
The parameters are not used as the instructions are not yet widely
supported.
Keep definitions so they can be easily activated later.
Tracked in issue lowrisc/ibex#1228
Xcelium 19.03 doesn't support the `->` (binary logical) operator, but
using `|->` (overlapping implication) is equivalent here and supported;
use this operator instead.
Fixes#1213
These changes correspond to similar changes in the prefetch buffer to
support branch prediction. A registered version of fill_ext_done was
required to prevent a combinational loop from branch_i in to valid_o
out.
Multiplexing priorities for fifo_addr have been swapped to match
fetch_addr_d in the same module and all similar multiplexing in the
icache (prioritize incoming branch_i over branch_mispredict_i). Note
however that it is not expected that these conditions will actually
occur together, and an assertion has been added to check that.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Remove the SpeculativeRequest parameter, and replace it with a
policy. If the cache is disabled, make the request on the basis that we
definitely won't hit in the cache and so should make the bus request
asap.
Stop fill buffers from fetching complete cache lines when the cache is
disabled. When the core branches into the middle of a line, the lower
words would normally be fetched to complete the line. This is
unnecessary when the cache is disabled since those words will just be
thrown away and the core will stall while they are being fetched.
These two changes make the performance using the disabled icache the
same as using non-icache prefetch buffer.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Make sure performance counters only count retired, non-trapping
instructions excluding ebrk/ecall
- Rewire some signalling through the writeback stage to allow
instruction retire to be signalled from one place
- Relates to #1132
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Reduce the size of the PMP address configuration registers to the
permissible minimum depending on granularity.
- Ensure consistency between PMP address CSR reads and the addresses
forwarded to the PMP module.
- Follow the specification more strictly, by returning bits
pmpaddr[G-2:0] as all ones when pmpcfg.A[1] is set (i.e. mode is
NAPOT or NA4, though the latter is invalid for G > 0) and bits
pmpaddr[G-1:0] as all zeros when pmpcfg.A[0] is clear (i.e. mode is
OFF or TOR).
- Fixes#1181
- Generate correct masks for NAPOT range addresses covering the entire
granule. When PMPGranularity > 0, then a NAPOT range can span the
whole granule, which requires the next-lowest bit (i.e. highest bit
that is not part of the granule) to be 0.
- Fixes#1178
This PR makes changes to support Cadence Xcelium 20.09.001
Compile error 1: Fixed the following rtl compile error in ibex_cs_registers.sv
assign tselect_rdata = {'b0, tselect_q};
|
xmvlog: *E,NONOWD (/proj/riscv_ibex/users/paulok/lowRISC/ibex_1/rtl/ibex_cs_registers.sv,1288|30): Illegal use of a constant without an explicit width specification [4.1.14(IEEE)].
Compile error 2: Fixed the following DV compile error in ibex_mem_intf.sv
.data_req_o (data_mem_vif.request ),
|
xmelab: *E,ICDCBA (./tb/core_ibex_tb_top.sv,89|14): Illegal combination of driver and output clockvar to variable 'request' detected (output clockvar found in clocking block at line 25 in file ./common/ibex_mem_intf_agent/ibex_mem_intf.sv).
Simulation probes: Fixed issue with probing in yaml for xrun and added licqueue.
Signed-off-by: Paul OKeeffe <paul_okeeffe@crevinn.com>
