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126 commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Harry Callahan
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0c0626ebbf |
Update google_riscv-dv to google/riscv-dv@be9c75f
Update code from upstream repository https://github.com/google/riscv- dv to revision be9c75fe6911504c0e6e9b89dc2a7766e367c500 * Reserve one extra word when pushing GPRs to kernel stack (Harry Callahan) * Store user-stack-pointer on kernel stack when pushing/popping GPRs (Harry Callahan) Signed-off-by: Harry Callahan <hcallahan@lowrisc.org> |
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Harry Callahan
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639f563a47 |
Update google_riscv-dv to google/riscv-dv@ada58fc
Update code from upstream repository https://github.com/google/riscv- dv to revision ada58fc57a6bc1265e6c261b0f468a79c946a640 * [pmp] Fix plusarg detection for MML and MMWP (Marno van der Maas) * [pmp] Add missing line return (Marno van der Maas) * [pmp] Improve formatting of PMP addresses for debug (Marno van der Maas) * [pmp] Add a register for loop counter in PMP traps instead of mscratch (Marno van der Maas) * [pmp] Add illegal TOR and NAPOT address mode constraints (Marno van der Maas) * [pmp] Try to skip instruction if no PMP match and in MMWP (Marno van der Maas) * [pmp] Store and load faults caused by locked PMP regions now skip to next instruction (Marno van der Maas) * [pmp] Check for MML before modifying PMP entry in trap handler (Marno van der Maas) * [pmp] Allow already configured addresses to be overwritten with plusargs (Marno van der Maas) * [pmp] Use kernel_inst_end for end of code entry (Marno van der Maas) * [pmp] Add end of kernel stack to stack entry (Marno van der Maas) * [pmp] Put signature and stack in last PMP entries (Marno van der Maas) Signed-off-by: Harry Callahan <hcallahan@lowrisc.org> |
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Canberk Topal
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33f1d0a702 |
Update google_riscv-dv to google/riscv-dv@e0eae9e
Update code from upstream repository https://github.com/google/riscv- dv to revision e0eae9e0ca69770c519c82c48421005f65521eac * [sv] Explicit type casting for VCS compability (Canberk Topal) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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Harry Callahan
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25d81afef6 |
Update google_riscv-dv to google/riscv-dv@c6acc18
Update code from upstream repository https://github.com/google/riscv- dv to revision c6acc1897429f5245cc89b2ecee2e3eefdefd18d * Add plusarg to enable ECALL insn in main randomized body (Harry Callahan) Signed-off-by: Harry Callahan <hcallahan@lowrisc.org> |
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Greg Chadwick
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494438dc4e |
Update google_riscv-dv to google/riscv-dv@9c2b007
Update code from upstream repository https://github.com/google/riscv- dv to revision 9c2b007eea5baed25dc9b4c3181c2f328f98a2af * [pmp] Add knob to suppress PMP setup code (Greg Chadwick) Signed-off-by: Greg Chadwick <gac@lowrisc.org> |
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Michael Schaffner
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bbde00d174 |
Update lowrisc_ip to lowRISC/opentitan@d1be61ba8
Update code from upstream repository https://github.com/lowRISC/opentitan to revision d1be61ba88a145e882df4e7c7a47f78bcf2371f8 * [testplanner] Replace IP milestone terminology with development stage (Michael Schaffner) * [doc] Replace IP milestone terminology with development stage (Michael Schaffner) * [prim] Fix missing case from prim_reg_cdc_arb assert (Timothy Chen) * [tools/dv] Remove set_fsm_reset_scoring coverage directive from common.ccf (Steve Nelson) * [dv] Exclude FSM transitions that can only happen on reset (Weicai Yang) * [chip dv] Fixes for chip level falures (Srikrishna Iyer) * [dv, mem_bkdr_util] Add system base addr (Srikrishna Iyer) * Switch to run-time options instead (Timothy Chen) * [dvsim] Fix coverage upload URL (Michael Schaffner) * [prim] Tweak code slightly to avoid UNR entries (Timothy Chen) * [prim] Add () to s_eventually (Timothy Chen) * [dvsim] Add python workaround for shutil (Michael Schaffner) * [dvsim] Make sure odir is of type Path (Michael Schaffner) * [dvsim] Fix bug causing error in existing odirs (Canberk Topal) * [prim] More refactoring to remove UNR generation (Timothy Chen) * [dvsim] Fix flake8 lint warnings (Michael Schaffner) * [dvsim] Align local and server path structure (Michael Schaffner) * [dvsim] Remove support for email report (Michael Schaffner) * [dvsim/doc] Place summary results into separate hierarchy (Michael Schaffner) * [dvsim/utils] Fix a typo (Michael Schaffner) * [dvsim] Default report folder name to 'latest' (Michael Schaffner) * [dvsim] Use relative links on summary page (Michael Schaffner) * [xcelium warning] Cleanup unexpected semicolon warning (Srikrishna Iyer) * [dv/mem_bkdr] Fix digest update (Timothy Chen) * [dvsim] Handle same test added twice via `-i` (Srikrishna Iyer) * [lint] Fix shellcheck errors in hw (Miles Dai) * [sw/silicon_creator] Rename mask_rom to rom (Alphan Ulusoy) * [spi_device/dv] Fix payload check (Weicai Yang) * [dvsvim] ensure ELF file with proper ext gets copied to `run_dir` (Timothy Trippel) * [prim] Assertion update for prim_reg_cdc (Timothy Chen) * [prim_lfsr dv] Designate a primary build (Srikrishna Iyer) * [dv] Increase stress tests run time limit to 3h (Weicai Yang) * [dvsim] Fix run timeout override in hjson (Srikrishna Iyer) * [dv/cov] Exclude some prim modules from detailed coverage (Guillermo Maturana) * [prim,dv] Reg CDC hardware request fix (Canberk Topal) * [prim] Add more lint waivers (Michael Schaffner) * [dvsim] Add support for specifying primary_build_mode (Srikrishna Iyer) * [dv] Add some VCS coverage options (Srikrishna Iyer) * feat(kmac): Add FI attack protection on packer pos (Eunchan Kim) * [dv] small fix at mem_model (Weicai Yang) * [dvsim] enable manufacturer tests to run in DV sim (Timothy Trippel) * [dvsim] Fix errors due to test duplication (Srikrishna Iyer) * [pad_wrapper] Do not model keeper (Michael Schaffner) * [lint] Fix several SAME_NAME_TYPE errors (Michael Schaffner) * [flash_ctrl] Lint fix (Michael Schaffner) * [dvsim] Include error message cotext (Srikrishna Iyer) Signed-off-by: Michael Schaffner <msf@google.com> |
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Marno van der Maas
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4990aa2684 |
Update google_riscv-dv to google/riscv-dv@68e3bca
Update code from upstream repository https://github.com/google/riscv- dv to revision 68e3bcac7293ac79067f0d8196bb973bd7c889cf * [pmp] Remove restriction on using NAPOT when granularity = 0 (Marno van der Maas) * [pmp] Add PMP entries for data in case of MML or MMWP (Marno van der Maas) * [pmp] Add already_configured flag to skip address in PMP routine (Marno van der Maas) * [pmp] Fix constraint and CSR write test in MML mode (Marno van der Maas) * [pmp] Use random address instead of offset for full random test (Marno van der Maas) * [pmp] Allow specifying address zero in `+pmp_region_%0d` (Marno van der Maas) * [pmp] Randomizing entry for instructions for PMP randomization (Marno van der Maas) * [lint] Remove trailing whitespace (Marno van der Maas) * Tweak CSR constraints for more even read/write distribution (Greg Chadwick) * [lint] Replace tabs with spaces (Marno van der Maas) * [pmp] No PMP exception handler when no PMP support (Greg Chadwick) * Expand CSR instruction constraint functionality (Greg Chadwick) * Refactor CSR instruction into their own class (Greg Chadwick) Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org> |
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Marno van der Maas
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90a81a3cc7 |
Update lowrisc_ip to lowRISC/opentitan@f9e667550
Update code from upstream repository https://github.com/lowRISC/opentitan to revision f9e6675507fdd81e0b0dd3481c0a4bca634f322d * [ralgen] Minor correction in alias-file passing mechanism (Michael Schaffner) * [entropy_src/dv] Track FW_OV FIFO exceptions (Martin Lueker-Boden) * [dv/clkmgr] Fix reset handling (Guillermo Maturana) * [flash_ctrl] Add generic registers for the flash wrapper (Michael Schaffner) * [fpv/prim_onehot_check] Fix prim_onehot_check compile error (Cindy Chen) * [dvsim] Minor cleanup of job_runtime updates (Srikrishna Iyer) * [chip/dv] replace wait with DV_WAIT (Weicai Yang) * [dv] Add DV_WAIT macro (Weicai Yang) * [dvsim] Display max CPU time in regression result (Cindy Chen) * [dv, xcelium] Indicate SVA-disabled hierarchies (Srikrishna Iyer) * [dv, xcelium] Update switches, sim finishi (Srikrishna Iyer) * [utils,dvsim] Add wall-clock timeout feature (Guillermo Maturana) * [prim_count] This reworks the primitive to make it more generic (Michael Schaffner) * [dvsim] remove unecessary `sw_build_dir` parameter (Timothy Trippel) * [dvsim] use Bazel labels for SW images (Timothy Trippel) * [entropy_src/dv] Refactor entropy_src_rng_vseq (Martin Lueker-Boden) * [dv, waves] Improve wave dumping (Srikrishna Iyer) * [dv/kmac] Fix EDN timeout assertion failures (Cindy Chen) * [doc] Move style guides into a separate section (Miguel Osorio) * [spi_device/dv] Enable testing SFDP command (Weicai Yang) * [doc] Unlist dangling pages from menus. (Miguel Osorio) * [doc] Add DV intermediate sections (Miguel Osorio) * [doc] Skip markdown templates from the build (Miguel Osorio) * [dv/verilator] Fix numeric base of simulation statistics (Andreas Kurth) * [dvsim] Make email.html filename more descriptive (Srikrishna Iyer) * [csrng/dv] Add deposit to force states when disabled (Steve Nelson) * fix(rdc): typo (Eunchan Kim) * fix(rdc): Include NEW violations only to report (Eunchan Kim) * [dvsim] Add support for SW (bazel) build opts (Srikrishna Iyer) * fix(cdc): Parse NEW violations only (Eunchan Kim) * feat(rdc): Add Meridian RDC log parser (Eunchan Kim) * feat(rdc): Add Meridian RDC flow to dvsim (Eunchan Kim) * [dv/cip_base] Add checking in stress_all_with_rand_reset seq (Cindy Chen) * [clkmgr/prim] Make frequency measurement disable more robust (Timothy Chen) * [prim/lint] Update waivers (Michael Schaffner) * [doc] Update D2 checklist (Michael Schaffner) * [clang-format] Format all covered files (Alexander Williams) * [dvsim] Indicate what is currently running (Srikrishna Iyer) * [doc] Fix trailing whitespace on md files. (Miguel Osorio) * [doc] Remove README.md files from hw,utils folders (Miguel Osorio) * [tools/dv] Modify common.ccf file for proper expression coverage (Steve Nelson) * [prim_edn_req] Accumulate repetition errors until the data is consumed (Pirmin Vogel) * [chip dv] Cleanup task invoked in func warning (Srikrishna Iyer) * [topgen] Pass alias register paths into topgen for top RAL generation (Michael Schaffner) * [dv] Split debug_access opt to another hjson variable for override (Weicai Yang) * [dv] Fix ping exclusion (Weicai Yang) * [prim] update register CDC scheme (Timothy Chen) * [dv] Add assertion to check reg_we onehot error leads to a fatal alert (Weicai Yang) * [sw,tests] Test flash_ctrl init and scramble (Dave Williams) * [PRIM] new clock mux to prevent a glitch (Joshua Park) * [dv] Add prim_cdc_rand_delay exclusion in cover_reg_top (Weicai Yang) * [prim] Add additional qualification to the trigger (Timothy Chen) * [prim] Add description to parameters (Timothy Chen) * [sw,tests] Add -f option to copy in sim.mk (Dave Williams) * [top/spi_device] constraint and clock updates (Timothy Chen) * [dv] Update xcelium coverage config file (Weicai Yang) * fix(prim): High memory usage of Assertion (Eunchan Kim) * [top,dv] rv_dm agent update (Jaedon Kim) * [dv] Enable reg_wr_check test for all blocks (Weicai Yang) * [dv] Update tl testplan for reg write enable check (Weicai Yang) * Refixed 12236 to a more rubust solution (Rasmus Madsen) * [fpv/alert_handler] Add sec_cm FPV testbench for alert_handler (Cindy Chen) * [dv,ralgen] revert `ralgen.py` to use relative file paths (Timothy Trippel) * [dv,ralgen] update `ralgen.py` to use git paths over relative (Timothy Trippel) * doc(prim): Specify ICEBOX for prim_packer (Eunchan Kim) * [bazel,dvsim] update dvsim.py to use Bazel to build SW (Timothy Trippel) * [prim] Added generic xnor2 (Arnon Sharlin) * [flash_ctrl/prim_flash] Add parameters to tweak module latency (Timothy Chen) * [prim_assert] Fix ASSERT_FPV_LINEAR_FSM (Guillermo Maturana) * [chip,rstmgr,dv] regression fix rstmgr_alert_info test (Jaedon Kim) * [dv/tool] Collect csr assertion cov (Cindy Chen) * [otp_ctrl] Add generic registers for prim_otp_wrapper (Michael Schaffner) * [dvsim] Use leaf most field if conflict rather than Exception (Eunchan Kim) * [regtool] Extend UVM backend to support alias definitions (Michael Schaffner) * [fvp/pwrmgr] Pwrmgr fsm error (Cindy Chen) * [dvsim] Revert lowRISC/opentitan#12761 to build SW with meson (Timothy Trippel) * [bazel,dvsim] update dvsim.py to use Bazel to build SW (Timothy Trippel) * [prim] removed unused files (Timothy Chen) * [flash_ctrl] Harden FIFO pointers (Timothy Chen) * [dv] Remove TB_LINT_PASS in all IP checklists (Weicai Yang) * [dv/flash_ctrl] Temp fix flash_ctrl regression compile error (Cindy Chen) * fix(prim): Lint fix for line length (Eunchan Kim) * fix(prim): Lint warning for `err_o` (Eunchan Kim) * [dv] Fix Xcelium toggle collection (Weicai Yang) * [hw/ip] Add extra prim_fifo_sync port (Timothy Chen) * [prim/fifo] Add option to harden prim fifo pointers (Timothy Chen) * [dv_base_reg] Extend search by name functions (Michael Schaffner) * [fpv/lc_ctrl] Add gating conditions for sec_cm assertions (Cindy Chen) * [primgen] Sort the parameters (Weicai Yang) * [python] flake8 lint cleanups (Michael Schaffner) * [prim_subreg] Remove anchor bufs since they are not needed (Michael Schaffner) * [dv] Add `-xprop=mmsopt` run-opt for VCS (Weicai Yang) * [dv] Temporarily remove CDC assertions (Weicai Yang) * [hw/dv] further updated dv flow to now score systemverilog tasks and functions (Rasmus Madsen) * [dv/chip] Fix bit_bash timeout error (Cindy Chen) * [flash_ctrl] Allow fixed priority arbiter (Timothy Chen) * [prim_assert] Minor rewording in comment (Michael Schaffner) * [dv/xcelium] 1 attempt of cleaning up the coverage files (Rasmus Madsen) * [dvsim] revert lowRISC/opentitan#12319 to fix CI (Timothy Trippel) * [primgen] Sort the parameters to ensure stable order (Weicai Yang) * [prim] Fix python style (Weicai Yang) * [bazel] update dvsim.py to build ROMs with bazel (Timothy Trippel) * [dvsim] Correct argparse usage statement and help (Drew Macrae) * [prim_assert] Fix assertion include order (Michael Schaffner) * [ast] Lint fixes and waiver updates (Michael Schaffner) * [prim/lc_ctrl] Create a common assertion macro for linear FSM check (Michael Schaffner) * [dv/csr_utils] Clean up mem_rd/wr print out message (Cindy Chen) * [doc] Update D3 checklist per RFC (Michael Schaffner) * [prim_dom_and_2share] Allow re-use of intermediate results for remasking (Pirmin Vogel) * [prim_dom_and_2share] Add parameter to enable full/optional pipelining (Pirmin Vogel) * [dv/vcs] Update cdc exclusion keyword (Cindy Chen) * [prim] Add a duplicated prim_arbiter instance (Timothy Chen) * [dv/cdc assertion] Temp remove CDC assertion cov collection in VCS (Cindy Chen) * [prim_onehot_check] Rework lint fix (Michael Schaffner) * [mubi/lc_ctrl] Change MUBI / lc_tx_t encodings (Michael Schaffner) * [dv] Update xcelium cover.ccf to only enable coverage for dut (Weicai Yang) * [dv/xcelium] Fix Xcelium nightly regression error (Cindy Chen) * [prim_onehot_mux] Add lint waivers (Michael Schaffner) * [prim_lc_sender] Add waiver (Michael Schaffner) * [prim_mubi] Make sure waiver file is listed in core file (Michael Schaffner) * [tlul_fifo_async] Move waiver to correct file and remove old waivers (Michael Schaffner) * [prim_blanker] Remove prim_and2 waiver file (Michael Schaffner) * [prim_packer] Lint fixes (Michael Schaffner) * [prim_secded] Add lint waiver file (Michael Schaffner) * [dv/cov] Exclude CDC module from collecting coverage (Cindy Chen) * [reggen] Add spurious WE check to autogen'd regfile (Michael Schaffner) * [prim_reg_we_check] Add spurious CSR write checker (Michael Schaffner) * [prim_onehot_check] Add option for permissive en_i checks (Michael Schaffner) * [tools/dv] updated UNR flow to support xcelium/jg (Rasmus Madsen) * [prim] Add dv_macros missing dependency (Timothy Chen) * [top, dv] Fix ext clk plusarg (Weicai Yang) * [dv/build_seed] Fix build_seed (Cindy Chen) * [clkmgr] Correct the disable condition (Timothy Chen) * [flash, dv] Fix RMA test backdoor symbol overwrite (Weicai Yang) * [top, dv] Fix rom backdoor symbol overwrite (Weicai Yang) * [flash_ctrl] Add checks for unexpected acks (Timothy Chen) * [prim_present] Add Verilator lint waiver (Michael Schaffner) * [xcelium] Pass cov_merge_db_dir through to cov_report.tcl (Rupert Swarbrick) * [dv/build_seed] Fix build seed errors (Cindy Chen) * [prim_mubi] Add assertion to check that the values are complementary (Michael Schaffner) Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org> |
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Marno van der Maas
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5b15f7aad1 | [vendor] Update patch file based on upstream OpenTitan | ||
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Marno van der Maas
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b98efe7cbe |
Update google_riscv-dv to google/riscv-dv@808fb16
Update code from upstream repository https://github.com/google/riscv- dv to revision 808fb162d66de5dd0dd2b45fd0b8d1fb1bf170f6 * [scripts] Improve WARL support in gen_csr_test (Greg Chadwick) * [scripts] Refactor gen_csr_test (Greg Chadwick) * Allow for WFI in User Mode (Canberk Topal) * [Smepmp] Fixes `gen_pmp_instr` when MML and MMWP are enabled (Marno van der Maas) * Fix typo in mseccfg_reg_t class (aneels3) * Fix google/riscv-dv#819 (aneels3) * lib.py, launch process in new session to fix timeout issue (Yannick Casamatta) Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org> |
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Marno van der Maas
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7f1bdcd5a2 | [vendor] Remove patch that has been upstreamed | ||
Pirmin Vogel
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f71b23ddf8 |
Update google_riscv-dv to google/riscv-dv@0b2b3d6
Update code from upstream repository https://github.com/google/riscv- dv to revision 0b2b3d65ce8fdff4de8974d1f328a90d6c1db5dd * [epmp] Add support for mseccfg CSR (Pirmin Vogel) Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org> |
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Pirmin Vogel
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223f7cd25b |
Update google_riscv-dv to google/riscv-dv@cc4b870
Update code from upstream repository https://github.com/google/riscv- dv to revision cc4b87057cb38c91cb0c2ecb065e38281df7aa97 * Fix google/riscv-dv#857 (aneels3) * [euvm] Fixed a typo in the README file (Puneet Goel) * [euvm] updated the README file (Puneet Goel) * [euvm] Moved euvm specific README to euvm folder (Puneet Goel) * [euvm] ported some SV updates (Puneet Goel) * [euvm] Fixed generated ASM code indentation (Puneet Goel) * Add support for RV64IMC instr coverage (aneels3) * Add register definitions for privilege spec 1.12 and debug spec 1.0.0 (Henrik Fegran) * Updated README note for EUVM (Puneet Goel) * Use current date in output folder name (Puneet Goel) * Try to create output file folder if it does not exist (Puneet Goel) * Added a readme for EUVM port (Puneet Goel) * Allow providing a randomization seed from command line (Puneet Goel) * Make merging of directed instruction streams scalable (Puneet Goel) * Create and use new class riscv_prog_instr_stream (Puneet Goel) * Added and used append and prepend functions for instr_list (Puneet Goel) * Added new targets and tests (Puneet Goel) * Expose riscv instruction classes in the riscv gen package (Puneet Goel) * Use mixin templates to create RISCV instruction classes (Puneet Goel) * Fix a bug in asm section tag generation (Puneet Goel) * EUVM upgrade for bitmanip (Puneet Goel) * Use new clog2 implemented in esdl.data.bvec module (Puneet Goel) * Add debug and clean targets to Makefile (Puneet Goel) * Use Queue functions in place of array concatenation (Puneet Goel) * Misc fixes after review (Puneet Goel) * Fix broken run.py script (Puneet Goel) * Use more verbose naming in main function in the test (Puneet Goel) * Removed some redundant code comments (Puneet Goel) * Allow verbosity and instr count specification from make run command (Puneet Goel) * Handle riscv_loop_instr confliting constraint in post_randomize (Puneet Goel) * Use variable names that do not conflict with outers (Puneet Goel) * Use constraint in place of Constraint (Puneet Goel) * Fixed a typo where '-' was getting printed in place of ' ' (Puneet Goel) * Pick urandom from new location -- esdl.base.rand (Puneet Goel) * Fixed an issue where newline character was not getting added to some instructions (Puneet Goel) * Fixed an issue with sup program generation (Puneet Goel) * Added EUVM riscv_instr_base_test (Puneet Goel) * Added EUVM riscv_instr_register module (Puneet Goel) * Moved EUVM files to euvm folder (Puneet Goel) * Add makefile command to to run a test (Puneet Goel) * Cast return value from ceil to integer (Puneet Goel) * Miscelleneous fixes (Puneet Goel) * Fixed some issues in riscv_loop_instr (Puneet Goel) * Use variable for setting rand_mode (Puneet Goel) * Use false in place of '0' for bools (Puneet Goel) * Added build makefile (Puneet Goel) * misc fixes (Puneet Goel) * Added riscv instruction definitions (Puneet Goel) * Added euvm module riscv_instr_registry (Puneet Goel) * Added euvm module riscv_data_page_gen (Puneet Goel) * Added euvm module riscv_privileged_common_seq (Puneet Goel) * Added euvm module riscv_debug_rom_gen (Puneet Goel) * Use urandom!bool in place of inappropriately named function toss (Puneet Goel) * Added euvm module riscv_illegal_instr (Puneet Goel) * Added euvm module riscv_asm_program_gen (Puneet Goel) * Use esdl.rand: toss instead os uniform(0, 2) (Puneet Goel) * Fixed randomization of avail_regs in euvm module riscv_instr_stream (Puneet Goel) * Use esdl.rand: shuffle instead of randomShuffle (Puneet Goel) * Added euvm module riscv_directed_instr_lib (Puneet Goel) * added euvm module riscv_load_store_instr_lib (Puneet Goel) * urandom has moved to package esdl.rand (Puneet Goel) * Added euvm module riscv_instr_sequence (Puneet Goel) * Added euvm module riscv_amo_instr_lib (Puneet Goel) * Added euvm module riscv_instr_stream (Puneet Goel) * A small fix in riscv_pmp_cfg module (Puneet Goel) * Added euvm module riscv_loop_instr (Puneet Goel) * Added euvm module riscv_pseudo_instr (Puneet Goel) * Added euvm module riscv_vector_instr (Puneet Goel) * Added euvm module riscv_floating_point_instr (Puneet Goel) * Added euvm module riscv_b_instr (Puneet Goel) * Added euvm module isa/riscv_compressed_instr (Puneet Goel) * Added euvm module isa/riscv_amo_instr (Puneet Goel) * Added euvm module isa/riscv_instr (Puneet Goel) * Added euvm module riscv_callstack_gen (Puneet Goel) * Added euvm module riscv_page_table_list (Puneet Goel) * Used ranged switch case statements where required (Puneet Goel) * Added euvm module riscv_privil_reg (Puneet Goel) * Add @UVM_DEFAULT uda on the class members where required (Puneet Goel) * Added euvm module riscv_reg (Puneet Goel) * Added euvm module riscv_pmp_cfg (Puneet Goel) * Added euvm module riscv_vector_cfg (Puneet Goel) * Added euvm module riscv_page_table_exception_cfg (Puneet Goel) * Added euvm module riscv_page_table_entry (Puneet Goel) * Added euvm module riscv_page_table (Puneet Goel) * Added riscv_core_setting module (Puneet Goel) * Added new file riscv_instr_gen_config (Puneet Goel) * Fixed some module imports (Puneet Goel) * Added new file riscv_signature_pkg (Puneet Goel) * Added D port of riscv_instr_pkg (Puneet Goel) Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org> |
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Michael Schaffner
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91745a076c |
Update lowrisc_ip to lowRISC/opentitan@1740ccd1a
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 1740ccd1ad19f83bf2cec120c87b807b9af2ca1b * [prim_onehot_check] Add address-based check (Michael Schaffner) * [flash_ctrl] convert flash config to mubi (Timothy Chen) * [sw,tests] Enter RMA LC_STATE and check flash access and wipe (Dave Williams) * [prim_onehot_check] Add lint waivers (Michael Schaffner) * [prim] Stub out guts of prim_cdc_rand_delay for Verilator (Rupert Swarbrick) * [prim] Add missing waiver (Timothy Chen) * [prim_onehot_check] Add prim_onehot_check (Michael Schaffner) * [dv] Add TL error case - write with instr_type = True (Weicai Yang) * [cdc-rand] Enable CDC random delay injection (Srikrishna Iyer) * [fpv/pinmux] Add tl integrity error check (Cindy Chen) * [prim_assert] Add static assertion macro for checks in pkgs (Michael Schaffner) * [prim] Add prim_blanker (Greg Chadwick) * [prim, rtl] Add new onehot primitives (Greg Chadwick) * [dvsim] Fix looping through old result directories (Cindy Chen) * [chip dv] Fixes for tests failing in nightly (Srikrishna Iyer) * [present] Rewrite TB to avoid non-freely licensed code (Rupert Swarbrick) * [secded_gen] Fix a bug in inverted Hamming codes (Michael Schaffner) * [prim,rtl] Fix RW collision bug in prim_1p_ram_scr (Greg Chadwick) * [dvsim,xcelium] Fix sed commands to generate plusargs (Rupert Swarbrick) * [dvsim,xcelium] Split two plusarg strings (Rupert Swarbrick) * [dvsim] Add a missing newline to error message (Rupert Swarbrick) Signed-off-by: Michael Schaffner <msf@google.com> |
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Canberk Topal
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9acd2583e1 |
Update google_riscv-dv to google/riscv-dv@6e0dc18
Update code from upstream repository https://github.com/google/riscv- dv to revision 6e0dc183a4678bfd581c1021b5ab7705f31d14a5 * [XCelium] Enable coverage collection with XCelium (Canberk Topal) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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Canberk Topal
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d659c96cda |
Update lowrisc_ip to lowRISC/opentitan@3a33c4df2
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 3a33c4df2ed31b0d7a8936531a4ae9a275177f1b * [prim,rtl] Pass addr_i in no scrambling case (Canberk Topal) * [dvsim,xcelium] Avoid an OPTP2ND error if a plusarg isn't set (Rupert Swarbrick) * [dv,tcl] Merge Coverage Databases with union_all (Canberk Topal) * [prim_count] Add missing include (Pirmin Vogel) * [sram_ctrl] Additional write gating based on intg error (Michael Schaffner) * [sram_ctrl] Remove nonce reversal to improve timing (Michael Schaffner) * [sram_ctrl] Retime address mux to improve timing (Michael Schaffner) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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Pirmin Vogel
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fe3e029108 |
Update google_riscv-dv to google/riscv-dv@cb4295f
Update code from upstream repository https://github.com/google/riscv- dv to revision cb4295f9ce5da2881d7746015a6105adb8f09071 * Update list search (Matthew Ballance) * Trap and report exceptions encountered in sub-processes and propagate error back (Matthew Ballance) * Workaround fix for loop test colon issue (aneels3) * Fix typo (aneels3) * Add support for RV64AFD (aneels3) * Fix typo (aneels3) * Update README.md (aneels3) * Add support for sub_programs (aneels3) * fix issue with imm value for 64 bit instr (aneels3) * Allow for underscores and capital letters in ISA for ISS (Pirmin Vogel) * implement rv64i (shrujal20) * Add support for RV32FD coverage (aneels3) * Integrate random seed for pyflow (aneels3) * Add riscv_loop_test (ShraddhaDevaiya) Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org> |
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Canberk Topal
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4c1a4ed1df |
Update lowrisc_ip to lowRISC/opentitan@0747afbdd
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 0747afbddec0ad176980429fe3100b32edb71d4a * [dv] Enable C/C++ code sourcing with VCS in .core (Canberk Topal) * [dv/dv_base_reg] Remove duplicated `get_map_by_name` method (Cindy Chen) * [prim] Pulse Sync assertion to check input/output (Eunchan Kim) * [sparse_fsm_flop] Create flop macro to increase DV coverage (Michael Schaffner) * [dvsim] Make build-randomization opt-in (Srikrishna Iyer) * [xcelium] Fix compile error (Srikrishna Iyer) * [dv/cov] fpv_csr_assert only collect assertion coverage (Cindy Chen) * [dv/jtag] Fix chip_level jtag csr rw failure (Cindy Chen) * [rtl] Convert some non-ANSI parameters to localparams (Rupert Swarbrick) * [prim] Waive unused parameters for Verilator in prim_generic_otp (Rupert Swarbrick) * [prim] Make a variable widening explicit in prim_present.sv (Rupert Swarbrick) * [prim] Waive some ALWCOMBORDER Verilator warnings in prim_arbiter_* (Rupert Swarbrick) * [prim] Fix Verilator lint warnings in prim_gf_mult.sv (Rupert Swarbrick) * [prim] Make some widening comparisons explicit in prim_clock_*.sv (Rupert Swarbrick) * [prim] Waive unused EnableAlertTriggerSVA for verilator lint (Rupert Swarbrick) * [bazel,dvsim] Add build rules for dvsim.py (Timothy Trippel) * [prim] Fix a bunch of Verilator lint errors in prim_packer.sv (Rupert Swarbrick) * [prim_sparse_fsm_flop/lint] Move waiver to correct file (Michael Schaffner) * [rv_dm dv] Test drive compile-time seed (Srikrishna Iyer) * [dvsim] Introduce Verilog compile-time seeds (Srikrishna Iyer) * [dvsim] Treat `tests: ["N/A"]` as an ignored testpoint (Srikrishna Iyer) * [hw/dv] Removed colon from Questa build and run fail patterns. (David Pudner) * [hw/dv] Code review changes for running questa simulations. (David Pudner) * [hw/dv] Added apache license header to questa_initial_setup.sh. (David Pudner) * [doc/ug] Updated opentitan documentation to include information about Questa use. (David Pudner) * [hw/dv] Added Questa dvsim files (David Pudner) * [dv/unr] Blackbox common security modules from UNR flow (Cindy Chen) * [dv] Minor fix to error message in mem_model.sv (Rupert Swarbrick) * [keymgr] Update keymgr to use prim_edn_req (Timothy Chen) * [doc] Fix rendering of special characters in testplan table (Rupert Swarbrick) * [dv] enable tlul_assert for csr part2 (Rasmus Madsen) * [dv] Enable tlul_assert for CSR tests (Weicai Yang) * [dv] Add valid/ready req/ack coverage for push_pull agent (Weicai Yang) * [dv,verilator] Make multiple sim_ctrl extensions play nicely (Rupert Swarbrick) * [chip dv] Add AST initialization routine (Srikrishna Iyer) * [top] auto generate (Timothy Chen) * [reggen] Make field 'qe' behavior consistent (Timothy Chen) * [prim] IFDEF_CODE waiver in sparsefsm flop (Eunchan Kim) * [dv] Update checklist for all blocks (Weicai Yang) * [dv/entropy_src] Temp remove stress_all_with_rand_reset test (Cindy Chen) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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Prajwala Puttappa
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c900ef1476 |
Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7c4f8b3fde4bb625ac3330ff52d3f66507190fe5 Please note that we're adding push_pull_agent for the first time in this commit. Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org> |
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Prajwala Puttappa
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15da12dfd6 |
Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7c4f8b3fde4bb625ac3330ff52d3f66507190fe5 * Revert "[dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr" (Rupert Swarbrick) * [dv] Fix some signed/unsigned comparison warnings (Rupert Swarbrick) * [dv] Make an implicit up-conversion explicit (Rupert Swarbrick) * [dv] Remove an unused array variable in prince_ref.h (Rupert Swarbrick) * [prim/security] Improve the code for prim_sparse_fsm security check (Cindy Chen) * [dv] Apply VCS option `-xprop=mmsopt` only when wave dump is off (Weicai Yang) * [all] variety of minor lint fixes (Timothy Chen) * [dv] Add options to improve VCS runtime (Weicai Yang) * [rv_dm] CSR test fixes (Srikrishna Iyer) * [dvsim] Fix pass/fail status for synthesis regression (Michael Schaffner) * [prim] Minor lint fixes for unused clocks / resets (Timothy Chen) * [dv] Flag illegal ENUMASSIGN warnings as errors (Michael Schaffner) * [flash_ctrl] Correct erase suspend interface behavior (Timothy Chen) * [rstmgr] Address several d2s review items (Timothy Chen) * [fpv/sec] Add some workaround logic for $cast keyword (Cindy Chen) * [dv] CSR seq lib - support for adapter-less RAL (Srikrishna Iyer) * [dv] Prepare codebase for UVM REG changes (Srikrishna Iyer) * [dv] Print computed CSR stuff in RAL (Srikrishna Iyer) * [dv] Allow CSR tests to run on custom RALs (Srikrishna Iyer) * [fpv/rom_ctrl] Check connectivity for alerts in rom_ctrl (Cindy Chen) * [prim] Add prim_and2 primitive (Pirmin Vogel) * [prim_dom_and_2share] Remove EnNegedge parameter (Pirmin Vogel) * [prim_dom_and_2share] Use prim_xor2 and prim_flop_en primitives (Pirmin Vogel) * [prim_dom_and_2share] Switch to single randomness input (Pirmin Vogel) * [util/dvsim] Fix confusing error message (Guillermo Maturana) * [dvsim] Minor changes to SynCfg results reporting (Michael Schaffner) * [fpv] V2S formal support (Cindy Chen) * [tools/xcelium] updated common coverage exclusions to exclude single bit correctly (Rasmus Madsen) * [dv] Clean up enable_reg_testplan (Weicai Yang) * [top] Hook-up flash/otp control and observation bus to ast (Timothy Chen) * [lint] Increase the unroll count (Eunchan Kim) * [entropy_src] Document & Implement THRESHOLD_SCOPE (Martin Lueker- Boden) * [AST] USB Observe, Clocks & POR_NI logic update (Jacob Levy) * [prim] Add new assertion macro for generating static lint errors (Pirmin Vogel) * [dv] csr_seq_lib fixes (Srikrishna Iyer) * [dv] dv_base_reg_block - Add special knobs (Srikrishna Iyer) * [dv] dv_base_mem - add special knobs (Srikrishna Iyer) * [prim] Move sec_cm assertion to an include file in prim_assert (Weicai Yang) * [flash_ctrl] Fixes for erase suspend (Timothy Chen) * [dv] exclude d_user.rsp_intg[6] for xcelium (Weicai Yang) * [prim_flop_en] Dependency fix (Michael Schaffner) * [dv] add mubi coverage for CSR and update reggen (Weicai Yang) * [prim] Add option for secure buffers in prim_mubi (Timothy Chen) * [prim] Add option for hand instantiated buffers for prim_flop_en (Timothy Chen) * [dv/shadow_reg] Move shadow_reg to V2S (Cindy Chen) * [prim_count] Updated comments to reflect all changes in lowRISC/opentitan#10378 (Michael Tempelmeier) * [dv] Teach ECC32 flavours of mem_area to write with integrity bits (Rupert Swarbrick) * [dv/shadow_reg] update milestone for shadow reg tests (Cindy Chen) * [checklists] Update V2S checklists (Srikrishna Iyer) * [tools/xcelium] updated xcelium flow to vcs for coverage test grading (Rasmus Madsen) * [prim] Add stub flops to remove lint warnings (Timothy Chen) * [dv] Add automatic covergroup for all regwen CSRs (Weicai Yang) * [dvsim] Add support for tags in testplan (Srikrishna Iyer) * [dv] Enable xcelium to include X for toggle coverage (Weicai Yang) * [dv] Clean up mem_bkdr_util__sram (Weicai Yang) * [util, testplan] Allow relative testplan imports (Srikrishna Iyer) * [prim] Add phase output to shadow register primitive (Pirmin Vogel) * [dv] Add assertion to check double_lfsr err triggers an alert (Weicai Yang) * [dv] Fix foundary failure (Weicai Yang) * [prim] update prim_count comment (Timothy Chen) * [prim_flop_2sync] Make the prim a standard non-generated prim (Michael Schaffner) * [dv/prim_max_tree] Fix xcelium compile error (Cindy Chen) * [dv] Fixes to enable foundry database pwrmgr_smoketest (Timothy Chen) * [dv] Add countermeasure verification for double_lfsr (Weicai Yang) * [dv] Update countermeasure verification (Weicai Yang) * [doc] Update V2S items (Weicai Yang) * [prim_max_tree] Remove dedicated FPV TB since all SVAs are embedded (Michael Schaffner) * [prim_max_tree/fpv] Add a simple formal testbench (Michael Schaffner) * [prim_max_tree] Create a primitive that calculates maxima (Michael Schaffner) * [dv] CSR / RAL model fixes (Srikrishna Iyer) * [uvmdvgen] bug fix (Srikrishna Iyer) * [dv] Fix some Xcelium warnings (Srikrishna Iyer) * [dv] Disable some benign warnings (Srikrishna Iyer) * [prim_mubi*_sender] Add option to omit sender flops (Michael Schaffner) * [dv, mem_bkdr_util] Fix ECC-computed backdoor WRs (Srikrishna Iyer) * [keymgr] sparsify the data control fsm (Timothy Chen) * [prim_lc_sender] Add AsyncOn parameter (Michael Schaffner) * [prim] Update behavior of prim_count (Timothy Chen) * [flash_ctrl] Minor fixes to flash foundry failure (Timothy Chen) * [sw,tests,pwrmgr] Improve synchronization (Guillermo Maturana) * [sw,tests] SRAM execution test DV integration (Dave Williams) * [dv] Update common_cov_excl to exclude d_user.rsp_intg[6] (Weicai Yang) * [otbn, dv] Added otbn_passthru_mem_tl_intg_err testcase (Prajwala Puttappa) * [rom_ctrl, dv] Fixes regression failures in rom_ctrl_passthru_mem_tl_intg_err (Prajwala Puttappa) * [dv/chip] Add jtag_csr_rw seq (Cindy Chen) * [chip dv] Remove xcelium build opt (Srikrishna Iyer) * [doc] Reorder D2S checklist items (Michael Schaffner) * [reggen] Add support for validation of RTL CM annotation (Michael Schaffner) * [all] various simple lint fixes (Timothy Chen) * [mem_bkdr,dv] Add missing type to otp_write_lc_partition_cnt (Rupert Swarbrick) * [dv/csr_utils_pkg] Clone ral map with top-level submaps (Cindy Chen) * [clkmgr] various spec and parameter updates (Timothy Chen) * [dv] Add ASSERT_NET to check net value (Weicai Yang) * [dv] revert lowRISC/opentitan#9050 and lowRISC/opentitan#9934 (Weicai Yang) * [primgen] Update AscentLint waiver in generated abstract prim wrappers (Pirmin Vogel) * [prim_generic] Fix lint errors (Pirmin Vogel) * [prim_count] Fix lint warnings (Pirmin Vogel) * [prim_alert_receiver] Fix ping during init sequence bug (Michael Schaffner) * [rom_ctrl, dv] Added passthru mem test (Prajwala Puttappa) * [prim_assert,dv] Use if condition in assert_init (Srikrishna Iyer) * [prim_filter_cnt] Make threshold runtime programmable (Michael Schaffner) * [prim_filter*] Optionally instantiate a 2-stage sync in prim_filter* (Michael Schaffner) * [dv] intg_err test cleanup and change passthru_mem_tl_intg_err to V2S (Weicai Yang) * [prim_xilinx] Replace KEEP with DONT_TOUCH attributes (Pirmin Vogel) * [sram/dv] Enable the integrity test for passthru (Weicai Yang) * [dv] Add integrity test for passthru mem (Weicai Yang) * [dv/tools] Fix alert ping exclusion (Cindy Chen) * [dv/mem_bkdr_util] added backdoor write of LC counter into LC partition in OTP (Dror Kabely) * [prim_pad_wrapper] Add dual pad wrapper for USB (Michael Schaffner) * [prim_clock_mux] Model generic mux with boolean ops (Michael Schaffner) * [prim_buf] Ensure generic primitives contain a logic cell (Michael Schaffner) * [prim_count] improved documentation and style (Michael Tempelmeier) * Revert "[dv] Replace fileset_partner flag with fileset_ast flag" (Michael Schaffner) * [dv] Replace fileset_partner flag with fileset_ast flag (Sharon Topaz) * [dv] Pass data_intg_passthru to dv_base_mem (Weicai Yang) * [dv/prim_alert] Add V3 item to testplan (Cindy Chen) * [dv/prim_count] Add an assertion to check max count stable (Cindy Chen) * [dv] Fix typo in uvmdvgen comment (Rupert Swarbrick) * [mem_bkdr_util] Use inverted integrity in rom_encrypt_write32_integ (Rupert Swarbrick) * [doc/checklist] Template fix (Cindy Chen) * [mem_bkdr_util,rom_ctrl] Fix how we call encrypt_sram_data (Rupert Swarbrick) * [rom/ram/xbar/otbn] Switch end-end bus integrity to inverted ECC codes (Michael Schaffner) * [dv/prim_alert_tb] Modify the seq to ensure alert always sends (Cindy Chen) * [dv,xcelium] Fix lowRISC/opentitan#4230: Xcelium compile error. (Timothy Trippel) * [dv/prim_alert] Add randomization in ping request sequence (Cindy Chen) * [prim_alert_receiver] Only check for ping requests after initialization (Michael Schaffner) * [doc] Update D2S checklist template and description (Michael Schaffner) * [prim_esc_receiver] Switch to standardized prim_count (Michael Schaffner) * [prim_count] Add option to disable the connection SVA (Michael Schaffner) * [otbn, rtl] Lint fixes (Greg Chadwick) * [sram/dv] Better support partial write in scb (Weicai Yang) * [dv/mem_bkdr_util] Fix ECC width error in OTP foundary test (Cindy Chen) * [secded/lint] Fix lint errors (Michael Schaffner) * [dv/prim_esc] Add more stimulus to reach coverage goal (Cindy Chen) * [alert_handler] Switch to sparse fsm primitive (Michael Schaffner) * [prim_sparse_fsm_flop] Add a parameter to disable SVA (Michael Schaffner) Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org> |
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Michael Schaffner
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045b5707c1 |
Update google_riscv-dv to google/riscv-dv@6053014
Update code from upstream repository https://github.com/google/riscv- dv to revision 605301400555c235564f9336cc5fc220af7e951c * [style] Break long lines in newly added files (Michael Schaffner) Signed-off-by: Michael Schaffner <msf@google.com> |
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Michael Schaffner
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804c538db2 |
Update lowrisc_ip to lowRISC/opentitan@be1359d27
Update code from upstream repository https://github.com/lowRISC/opentitan to revision be1359d27d0e826e28e6611f318c286253cd05f1 * [secded_gen] Enhance inverted ECC code (Michael Schaffner) * [rtl] Add CRC32 primitive (Greg Chadwick) * [syn/cdc] Minor flow fixes in CDC and syn scripts (Michael Schaffner) * [dv] Minor update on mem_model (Weicai Yang) * [dv/prim_alert] Clean up alert test (Cindy Chen) * [bazel] Build verilator with bazel (Chris Frantz) * [cdc] Add support for initial CDC flow with open-source views (Michael Schaffner) * [lc_ctrl/dv,dv_lib,dv_utils,csr_utils] Added JTAG CSR Infrastructure (Nigel Scales) * [prim] Add a lint waiver for dv-only code / ifdefs (Timothy Chen) Signed-off-by: Michael Schaffner <msf@google.com> |
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Pirmin Vogel
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d8e50dcc2c |
Update google_riscv-dv to google/riscv-dv@ea8dd25
Update code from upstream repository https://github.com/google/riscv- dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0 * Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00 (Pirmin Vogel) * Added v1.0.0 bitmanip support (Henrik Fegran) * Remove the pyucis-viewer from requirements.txt (aneels3) * Update README.md for PyFlow & add pyucis-viewer in requiremen.txt (aneels3) * Fix typo with fs3_sign (aneels3) * Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3) * override deepcopy method (aneels3) * Fix issue with illegal_instr_testi and randselect (aneels3) * Fixed b_extension_c() issue (shrujal20) * Fixed get_rand_spf_dpf_value() issue (shrujal20) * Add support for RV32C coverage (aneels3) * Add README.md for PyFlow (aneels3) * Add gen_timeout for PyFlow (aneels3) * Issue google/riscv-dv#778 fix, change mie behavior in setup_mmode_reg (Henrik Fegran) * Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions (Henrik Fegran) * Update riscv_compressed_instr.sv (AryamanAg) * Update var binary of function convert2bin (AryamanAg) * Improve status reporting (Philipp Wagner) * update ml/testlist.yaml to get better coverage (Udi Jonnalagadda) * add m extension covgroup (ishita71) * Update pygen_src files (aneels3) Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org> |
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Michael Schaffner
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4df2221dee |
Update lowrisc_ip to lowRISC/opentitan@34ba5e45f
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 34ba5e45f9af7d8ca6c9bdae8bd11eeeeb669d6c * [dv] Add new ECC code options to mem_bkdr_util (Michael Schaffner) * [secded_gen] Define and generate inverted ECC enc/dec modules (Michael Schaffner) * [dv] Only run registers through one csr_rw sequence at once (Rupert Swarbrick) * [alert_handler] Minor lint fix (Michael Schaffner) * [prim_clock_div] Fix minor Verilator lint warning (Michael Schaffner) * [dvsim/lint] Make message reporting more flexible (Michael Schaffner) * [lint] Unify lint parser scripts (Michael Schaffner) * [rom_cntrl, dv] Test to verify successful rom check (Prajwala Puttappa) * [dv, dv_macros] Enhance `DV_GET_ENUM_PLUSARG` macro (Srikrishna Iyer) * [sram/dv] Fix mem data check (Weicai Yang) * [prim] Add flop wrapper for sparse fsm (Timothy Chen) * [flash_ctrl] Make data / metadata memories a single entry (Timothy Chen) * [dv] Teach encrypt/decrypt_sram_data to support OTBN (Rupert Swarbrick) Signed-off-by: Michael Schaffner <msf@google.com> |
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Canberk Topal
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53b1732b19 |
Update lowrisc_ip to lowRISC/opentitan@3a672eb36
This commit also adds memory manipulation package in ibex repository. Update code from upstream repository https://github.com/lowRISC/opentitan to revision 3a672eb36aee5942d0912a15d15055b1d21c33d6 * [mubi] Fix path in auto-gen header (Rupert Swarbrick) * [dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr (Rupert Swarbrick) * [prim] Fix prim_ram_1p_scr Dependencies (Canberk Topal) * [dv/clk_rst_if] Split clk_rst_if jitter to 2 different values (Eitan Shapira) * [dv] Add external hjson path support in ralgen (Srikrishna Iyer) * [dv] Add sub RAL block creation knobs (Srikrishna Iyer) * [pwrmgr] Make rom_ctrl check signals multi-bit (Timothy Chen) * [dv/alert_handler] Randomize mubi input (Cindy Chen) * [flash_ctrl] Fix bank erase / info partition issue (Timothy Chen) * [ci] Fix CI failure (Weicai Yang) * [Cleanup] Remove lc_tx_e type and replace it with lc_tx_t (Weicai Yang) * [aes] Add gtech synthesis setup (Michael Schaffner) * [mubi] Enhance mubi_sync with stability check (Timothy Chen) * [prim] Fix prim_packer_fifo when ClearOnRead is false (Rupert Swarbrick) * [cleanup] Remove mubi4_e and replace it with mubi4_t (Weicai Yang) * [dv] Fix shape calculations for replicated ECC (Rupert Swarbrick) * [dv/alert] Support LPG in alert_sender/receiver pair (Cindy Chen) * [dv] Add a ReadWithIntegrity method to Ecc32MemArea (Rupert Swarbrick) * [dv] Simplify Ecc32MemArea read/write functions (Rupert Swarbrick) * [prim] Add option to not clear the packer FIFO upon read (Pirmin Vogel) * [dv] Change intg_err test from V3 to V2S (Weicai Yang) * [util] Delete generate_prim_mubi.py (Rupert Swarbrick) * [dv] Slightly generalise run_stress_all_with_rand_reset_vseq (Rupert Swarbrick) * [fpv] Fix some assumptions in prim_count (Cindy Chen) * [prim] quick path to prim_count assertion (Timothy Chen) * [dv] Support Multiple EDN Interfaces in OpenTitan (Canberk Topal) * [prim] Add xoshiro256pp primitive. (Vladimir Rozic) * [dv/prim_alert] Fix async fatal alert regression error (Cindy Chen) * [prim] Add missing include to prim_xilinx_pad_wrapper (Rupert Swarbrick) * [prim] Add missing include to prim_mubi_dec* (Rupert Swarbrick) * [dv/prim_alert_receiver] Fix assertion that consumes large mem (Cindy Chen) * [prim] Remove extra semicolon (Weicai Yang) * [chip,dv] Refactor CSR exclusion method (Srikrishna Iyer) * [top, all] update connects for mubi (Timothy Chen) * [flash_ctrl] Add plain text integrity in flash (Timothy Chen) * [prim] Add time-out functionality to prim_clock_meas (Timothy Chen) * [prim] Fix DC sythesis error (Weicai Yang) * [fpv] Fix regression failures (Cindy Chen) * [dv/ralgen] Update `dv_base_names` input from a string to a list (Cindy Chen) * [dv/ralgen] Update the `dv-base-prefix` optional input (Cindy Chen) * [doc] Add D2S and V2S checklist items to all checklists (Michael Schaffner) * [dv] Test security countermeasures (Weicai Yang) * [dv] Fix ASSERT_INIT race condition (Weicai Yang) * [syn/aes/otbn] Minor fixes to fix block level synthesis (Michael Schaffner) * [all] updated assert rtl ifdef (Timothy Chen) * [dv] Update TL intg testplan (Weicai Yang) * [prim] Add prim_fifo_async_sram_adapter to FPV list (Eunchan Kim) * [spi_device] Upload Cmd/Addr FIFO status revision (Eunchan Kim) * [dvsim] Modify resolve_branch to handle branch names with forward slash. (Todd Broch) * [prim_clock_inv] Add option to disable FPGA BUFG (Michael Schaffner) * [ralgen] Be more explicit which tool is called (Philipp Wagner) * [prim] Tweak prim_sync_reqack_data assertion so it can be disabled (Rupert Swarbrick) * [verible] Rename rule file (Philipp Wagner) * [dv/base_monitor] Cleaned up base monitor (Rasmus Madsen) * [fpv] prim_counter_fpv (Cindy Chen) * [dv/shadow_reg] Cross shadow reg error sequence with csr rw (Cindy Chen) * [dv] Fix scb multi-ral (Weicai Yang) * [dvsim] Enabling glob-style patterns for -i switch (Srikrishna Iyer) * [dv] Split sec_cm_testplan into multiple testplans (Weicai Yang) * [dv/dsim] Remove dsim's system_lib from library path (Guillermo Maturana) * [prim_packer] Resolve width mismatch (Philipp Wagner) * [prim] Fix lint error in prim_util_memload (Philipp Wagner) * [prim] Minor fix to make conn checks easy (Srikrishna Iyer) * [fpv] prim_secded FPV testbench updates bind file naming (Cindy Chen) * [dv_macros.svh] minor cleanup (Srikrishna Iyer) * [dv,xcelium] minor cleanup (Srikrishna Iyer) * [dv/shadowed_reset] Add a shadowed_rst_n interface (Cindy Chen) * [fpv] Update FPV file naming (Cindy Chen) * [top] Convert to mubi usage in some areas (Timothy Chen) * [entropy_src] mubi updates (Timothy Chen) * [prim] Add test for mubi invalid (Timothy Chen) * [prim_double_lfsr] Add duplicated LFSR primitive (Michael Schaffner) * [dv] Fix shadow reg backdoor path and enable csr_reset sequence (Weicai Yang) * [prim] Fix unused net (Timothy Chen) * [dv, clk_rst_if] Improve jitter and add scaling (Srikrishna Iyer) * [prim] Anchor buffers around register flip flops (Timothy Chen) * [alert_handler/top] Lint fixes and lc_tx_t to mubi4_t conversions (Michael Schaffner) * [prim_mubi] Replace true/false_value() functions with parameter (Michael Schaffner) * [dv/dsim] Get dsim to work at full chip (Guillermo Maturana) * [prim] Fixes for prim_count (Timothy Chen) * [top] Add various anchor points to modules (Timothy Chen) * [dv/pwrmgr] Add wakeup test sequence (Guillermo Maturana) * [reggen] Add mubi support into hjson (Timothy Chen) * [dv/shadow_reg] Fix aes shadow reg failure (Cindy Chen) * [dv/cdc] CDC simulation model (Udi Jonnalagadda) * [prim_lfsr/lint] Add temporary waiver for LOOP_VAR_OP lint error (Michael Schaffner) * [prim_clock_buf] Add lint waiver for unused parameter (Michael Schaffner) * [dvsim] Correctly set self_dir for included Hjson files (Philipp Wagner) * [util] Add tooling support for V2S milestone (Srikrishna Iyer) * [prim_mubi] Add decoder module similar to prim_lc_dec (Michael Schaffner) * [prim_mubi] Add mubi sender and sync primitives (Michael Schaffner) * [prim_mubi_pkg] Switch to True/False terminology (Michael Schaffner) * [prim] Minor work-around for xcelium (Timothy Chen) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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Rupert Swarbrick
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b66f199151 |
Update lowrisc_ip to lowRISC/opentitan@ad629e3e6
Update code from upstream repository https://github.com/lowRISC/opentitan to revision ad629e3e6e70c5eaa3c2dd68457b0a020448b35f * [dvsim] Introduce {self_dir} as variable (Philipp Wagner) * [dvsim] Small cleanups (Philipp Wagner) * [prim_lfsr] Minor lint fix (Michael Schaffner) * [dv] Update sec_cm testplan (Weicai Yang) * [prim/lint] Move waiver to correct waiver file (Michael Schaffner) * [prim_assert] Relocate waivers to dedicated prim_assert.waiver file (Michael Schaffner) * [alert_handler] Lint fixes and waiver updates (Michael Schaffner) * [prim_lc_receiver] Add parameter to select reset value (Michael Schaffner) * [lint] Add lint waiver for IP regfiles with shadow resets (Michael Schaffner) * [fpv] Fix Verible lint errors (Philipp Wagner) * [prim_lfsr] Minor lint fixes (Timothy Chen) * [clkmgr] Fix measurement control CDC (Timothy Chen) * [fpv/prim_counter] Pad one bit to include overflow case (Cindy Chen) * [fpv] Fix issue lowRISC#8371 (Zeeshan Rafique) * [flash_ctrl] Flash ctrl security hardening (Timothy Chen) * [dv] Fix CI error (Cindy Chen) * [prim_alert_*] Extend SVAs for FPV (Michael Schaffner) * [prim_alert_*] Update DV TB to respect initialization timing (Michael Schaffner) * [prim_alert_rxtx_fpv] Update FPV environment and fix SVAs (Michael Schaffner) * [prim_alert_sender] Update sender to support in-band reset mechanism (Michael Schaffner) * [prim_alert_sender] Simplify sender and clear ping req upon sigint (Michael Schaffner) * [prim_lc_sender] Add option to select reset value (Michael Schaffner) * [prim] Correct assertion valid term (Timothy Chen) * [prim_lc_combine] Align behavior of lc combine with mubi functions (Michael Schaffner) * [fpv/tool] Support GUI mode on dvsim (Cindy Chen) * [prim_lfsr] Further permutation refinements for SBox layer (Michael Schaffner) * [dv/shadow_reg] Shadow register write by field (Cindy Chen) * [prim] Fix the edge type (Eunchan Kim) * [checklist] Updates to checklist for D2 status (Tom Roberts) * [prim_mubi_pkg] Add a generic multibit type and associated functions (Michael Schaffner) * [prim] Minor fix and clarification to prim_count (Timothy Chen) * [keymgr/dv] Update testplan and covergroup plan (Weicai Yang) * [prim_lc_combine] Fix parameterization error (Michael Schaffner) * [fpv/prim_count] Small update on prim_count assertions (Cindy Chen) * [dv] Add ip_name in reg_block (Weicai Yang) * [keymgr] Finalize keymgr hardening (Timothy Chen) * [prim_lc_combine] Add a prim to compute logical AND/OR for LC signals (Michael Schaffner) * [dv] Remove common_cov_excl.el from unr.cfg (Weicai Yang) * [dv/top_level] Loop through the SW test multiple times (Cindy Chen) * [flash_ctrl] Various clean-up and updates (Timothy Chen) * [prim] Change prim_reg_cdc assertions (Timothy Chen) * [prim, keymgr] Migrate keymgr_cnt to prim_count (Timothy Chen) * [sw dv] Multi-site support for Verilator (Martin Lueker-Boden) * [dv/csr] Update write exclusion wdata value (Cindy Chen) * [dv/dv_base_reg] remove debug display (Cindy Chen) * [dv/shadow_reg] Fix alert shadow_reg regression error (Cindy Chen) * [top] Integrate ast into fpga (Timothy Chen) * [prim_lfsr] Improve statistics of non-linear output (Michael Schaffner) * [prim_esc_receiver] Fix response toggling corner case (Michael Schaffner) * option to use partner ast_pkg (Sharon Topaz) * [dv/prim_esc] Double the ping timeout cycles (Cindy Chen) * [dv] Use sed to add -elfile for each excl file (Weicai Yang) * [dv] Fix coverage report error (Weicai Yang) * [dv] Update common exclusion file (Weicai Yang) * [dv/prim_esc] Improve FSM coverage (Cindy Chen) * [reggen] Add a check to limit the swaccess type for shadow regs (Michael Schaffner) * [prim_subreg_shadow] Fix for W1S/W0C corner case (Michael Schaffner) * [prim_subreg_shadow] Disallow phase updates when storage err is present (Michael Schaffner) * [dvsim] Add passing count by milestone in reports (Srikrishna Iyer) * [dv/tool] Include toggle coverage for prim_alert_sender in cover_reg_top (Cindy Chen) * [clkmgr] Harden clock manager through frequency measurements (Timothy Chen) * [dv] Only enable VCS -kdb when dumping waves (Weicai Yang) * [dv] Fix shadow reg (Weicai Yang) * [dvsim] Allow non-integral values of --reseed-multiplier (Rupert Swarbrick) * [ast] Fixes for various ast issues (Timothy Chen) * [prim_esc_receiver] Assert escalation in case of sigint error (Michael Schaffner) * [prim_esc_receiver] Minor signal renaming for consistency (Michael Schaffner) * [dv/alert_handler] Support shadow register sequence (Cindy Chen) * [verilator] Use FileSz rather than MemSz when flattening ELF files (Michael Munday) * [prim_subreg_shadow] Only assert QE when committed_reg is written (Michael Schaffner) * [dv,verilator] Round up SV_MEM_WIDTH_BYTES to a multiple of 4 (Rupert Swarbrick) * [prim] Add missing include (Pirmin Vogel) * [dv/cover_cfg] Exclude prim_alert/esc from xcelium (Cindy Chen) * [dv/cover_cfg] Exclude prim_alert/esc pairs (Cindy Chen) * [clkmgr] Use local BUFHCE clock gates on FPGA (Pirmin Vogel) * [prim_prince] Mark "leaf" functions in prince_ref.h as static inline (Rupert Swarbrick) * [dv/shadow_reg] Check status after shadow_reg write (Cindy Chen) * [dv/shadwo_reg] Shadow reg common sequence update (Cindy Chen) * [otp_ctrl/lc_ctrl] Add 32bit OTP vendor test ctrl/status regs to LC TAP (Michael Schaffner) * [otp_ctrl] Add VENDOR_TEST partition (Michael Schaffner) * [prim] Edge Detector (Eunchan Kim) * [prim_diff_decode] Fix asynchronous assertions (Michael Schaffner) * [spi_device] Instantiate Upload module (Eunchan Kim) * [dv] Add sv_flist_gen_flags HJson var for FuseSoc (Srikrishna Iyer) * [dv, xcelium] Properly pass excl files to IMC (Srikrishna Iyer) * [reg] Fix shadow reg update during storage error (Timothy Chen) * [regfile] Refactor cdc handling to the reg level (Timothy Chen) * [dv/prim_esc] Add a testplan and increase coverage (Cindy Chen) * [dv] Update TLUL and EDN frequency (Weicai Yang) * [rstmgr, top] Add support for shadow resets (Timothy Chen) * [dv] Update Xcelium cover ccf (Srikrishna Iyer) * [dv] reduce seeds for CSR tests (Weicai Yang) * [usb/top] Remove AND gates on non-AON domain and rename 3.3V signal (Michael Schaffner) * [dv/prim_alert] Improvement on prim_alert tb (Cindy Chen) * [prim] FIFO SRAM Adapter fix (Eunchan Kim) * [prim] Add Write Mask port (Eunchan Kim) * [dv] Fix timescale issue with Xcelium (Weicai Yang) * [dv/prim_esc] Fix prim_esc regression error (Cindy Chen) * [dv/dv_base_reg] change from uvm_low to uvm_high (Cindy Chen) * [sram_ctrl] Harden initialization counter (Michael Schaffner) * [tools/uvmdvgen] Fix path in testplan inclusion (Guillermo Maturana) * [dv] Change stress_all_with_rand_reset to V3 (Weicai Yang) * [dv] fix tl error coverage (Weicai Yang) * [dv] Add macro DV_GET_ENUM_PLUSARG (Weicai Yang) * [prim] SRAM Async FIFO (Eunchan Kim) * [dv, xcelium] Fix statement coverage extraction (Srikrishna Iyer) * [dvsim] Minor fixes to coverage extraction (Srikrishna Iyer) * [prim_lfsr] Do not shadow |state| variable (Philipp Wagner) * [prim] Add non-linear out option to prim_lfsr (Timothy Chen) * [dv] Constrain TLUL to 24Mhz or higher (Weicai Yang) * [primgen] Instantiate tech libs in stable order (Philipp Wagner) * [primgen] Actually find the Verible Python wrapper (Philipp Wagner) * [dv/prim_esc] fix regression error (Cindy Chen) * [dv] Fix shadow reg predict (Weicai Yang) * [dv/common] Exclude assertion coverage from IP level testbench (Cindy Chen) * [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda) * [sram_ctrl] Update docs (Michael Schaffner) * [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner) * [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen) * [dv/dvsim] Add "testfile" grading option (Guillermo Maturana) * [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen) * [dv/utils] added 6MHz to clk_freq_mhz_e (Dror Kabely) * [prim_xor2/lint] Add waiver for .* use in generated prim (Michael Schaffner) * [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer) * Fix the testplan link in dvsim code (Srikrishna Iyer) * [dv/dsim] Add dsim workaround for issue 242 (Guillermo Maturana) * [util, reggen] Support standardized cdc handling for regfile (Timothy Chen) * [dv/shadow_reg] Align shadow_reg field update behavior (Cindy Chen) * [dvsim] Fix publish report summary typo (Cindy Chen) * [rtl/prim_alert_sender] Allow ping_req to stay high without error (Cindy Chen) * [dvsim] Separate publish report from dvsim flow [PART3] (Cindy Chen) * [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen) * [otp_ctrl] Connect test-related GPIO signal (Michael Schaffner) * [prim_subreg_shadow] Make local parameter a localparam (Philipp Wagner) * [prim_subreg] Make software access type an enum (Philipp Wagner) * [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen) * [otp_ctrl] Update AscentLint waiver file (Michael Schaffner) * [edn] Add MaxLatency assertion (Eunchan Kim) * [prim_subreg_shadow] Correct write data signal usage (Michael Schaffner) * [script/dvsim] Separate publish report from dvsim flow [PART2] (Cindy Chen) * [prim_lfsr] Fix assertion issue occuring right after reset (Michael Schaffner) * [dv/shadow_reg] Handle CSR automated sequence write abort (Cindy Chen) * [dv/dv_lib] Add post_apply_reset for extra delay (Guillermo Maturana) * [dv] Add function coverage plan for tl_errors, tl_intg_err (Weicai Yang) * [dv] Remove tl_intg_err in top-level and increase seeds for tl_intg_err (Weicai Yang) * [dv/shadow_reg] Fix alert shadow reg regression error (Cindy Chen) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Philipp Wagner
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d003d479ff |
Update lowrisc_ip to lowRISC/opentitan@da3ac7c4e
Update code from upstream repository https://github.com/lowRISC/opentitan to revision da3ac7c4eb23a92194874ad2daf2e5f9e3330572 * [memutil] Allow use without scrambled memories (Philipp Wagner) * [prim_prince] Fix comment (Philipp Wagner) * [memutil] Fix width mismatch (Philipp Wagner) * [prim] Allow disabling SVAs ensuring REQ is held until ACK at run time (Pirmin Vogel) * [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen) * [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert Swarbrick) * [dvsim] Do not assume the build failed if "ERROR" is printed (Philipp Wagner) * [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs (Michael Schaffner) * [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug (Michael Schaffner) * [primgen] Remove unused import (Philipp Wagner) * [primgen] Add shebang (Philipp Wagner) * [primgen] Make primgen "portable" again (Philipp Wagner) * [dv] Small optimization in memutil (Philipp Wagner) * [tools/ascent] updated ascent to use the --job-prefix option (Rasmus Madsen) * [otp_ctrl] Remove invalid command error (Michael Schaffner) * [tlul] Add some missing dependencies (Michael Schaffner) * [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael Schaffner) * [adc_ctrl] Various preparation steps for d2 (Timothy Chen) * [tools/dvsim] Fix some VCS flags (Guillermo Maturana) * Revert "[prim] Do remove prim_esc.core from the dependencies" (Rupert Swarbrick) * [prim] Remove dependency of prim:esc on a hardware block (Rupert Swarbrick) * [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick) * [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick) * [dv] Add C++ memory scrambling model (Greg Chadwick) * [tools/dsim] Fix non-LRM compliant code (Guillermo Maturana) * [prim] Do remove prim_esc.core from the dependencies (Michael Schaffner) * [dv/dv_utils] Improvement on `max` function (Cindy Chen) * [alert_handler] Implement reverse ping feature (Michael Schaffner) * [prim_esc] Split the prims into their own core file (Michael Schaffner) * [dvsim] Fix GUI mode and launcher creation fixes (Srikrishna Iyer) * [dv/common] Stress_all_with_rand_reset apply reset concurrently (Cindy Chen) * [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda) * [dv/csr_utils] update unmapped_addr calculation (Udi Jonnalagadda) * [dv] Update intg alert names (Weicai Yang) * [dv, flash_ctrl] Fix the intr test (Srikrishna Iyer) * [prim_fifo_async] Fix a width calculation issue in case of Depth = 1 (Michael Schaffner) * [dv] Update VCS opt for uvm_hdl_* (Weicai Yang) * [dv, util] Make poll_for_stop() opt-in (Srikrishna Iyer) * [dvsim] Separate publish report option [PART1] (Cindy Chen) * [dv/kmac/sram] reduce iterations of smoke test (Udi Jonnalagadda) * [dv/stress_all_with_reset] Revert back IPs that uses apply_reset (Cindy Chen) * [dv/edn_reset] Fix apply_reset to concurrently deassert resets (Cindy Chen) * [dv] Update VCS cov merge opts (Srikrishna Iyer) * [dv] Add TL integrity error test for CSR (Weicai Yang) * [dv, chip] Remove USB clk driver (Srikrishna Iyer) * [script/dvsim] Update output folder (Cindy Chen) * [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy Chen) * [dv/edn_reset] Fix stress_all_with_rand_reset error (Cindy Chen) * [dv/dv_base_scoreboard] remove duplicated code (Cindy Chen) * [otbn,dv] Teach otbn_memutil to track expected end address (Rupert Swarbrick) * [dv, dv_utils_pkg] Fix common int typedefs (Srikrishna Iyer) * [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner) * [prim_clock_gating] Target 7series Xilinx devices (Philipp Wagner) * [dv/edn_rst] Add coverage to collect edn reset and dut reset (Cindy Chen) * [otp_ctrl/lc_ctrl] Add LC TAP register to control OTP test mechanisms (Michael Schaffner) * [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops (Michael Schaffner) * [dv] fix a typo in tl_device_access_types_testplan (Weicai Yang) * [prim_otp] Rework generic model to match new error behavior (Michael Schaffner) * [dv/tlul_common_test] Add a testplan for TLUL integrity check (Cindy Chen) * [dvsim] Allow recursive testplan import (Srikrishna Iyer) * [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki) * [prim] Break always_comb block to avoid apparent loop (Rupert Swarbrick) * [dvsim] Fix testplan bugs (Srikrishna Iyer) * [fpv] update secded_gen (Cindy Chen) * [dv/template] small fixes on index.md format (Cindy Chen) * [prim_otp] Add a waiver for power signal unused in generic prim (Michael Schaffner) * [simutil_verilator] Improve timeout handling (Rupert Swarbrick) * [testplans] Rename entries with testpoints (Srikrishna Iyer) * [dvsim/testplan] Fix the rendered testplan (Srikrishna Iyer) * [dv/cov] exclude prim_lfsr and prim_prince (Udi Jonnalagadda) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Rupert Swarbrick
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e0b477069e |
Update lowrisc_ip to lowRISC/opentitan@7117c349d
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7117c349d5465b5152d3bb774079013924a3e9ba * [dv/common] Improve coverage exclusion method (Cindy Chen) * [prim] Waive unused parameter warnings for an FPGA-specific param (Rupert Swarbrick) * [dpi] Fix indexing bug in ecc32_mem_area (Rupert Swarbrick) * [dv, xcelium] Dump covergroup report (Srikrishna Iyer) * [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer) * [otp_ctrl] Workaround for generated prim depending on generated prim (Michael Schaffner) * [dpi_memutil] Fix bug in RegisterMemoryArea (Rupert Swarbrick) * [rom_ctrl/dv] Add skeleton testbench (Tom Roberts) * [dvsim/verilator] Remove FUSESOC_IGNORE (Michael Schaffner) * [checklists] Update all checklists for consistency (Srikrishna Iyer) * [dv] Add integrity generation to backdoor memory loading (Greg Chadwick) * [prim_secded] Add C reference models for Hsiao encode (Greg Chadwick) * [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy Chen) * [dv/unr] Fix unr clk rst ports (Cindy Chen) * [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin) * [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Philipp Wagner
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c7cb958f0d |
Update lowrisc_ip to lowRISC/opentitan@ca950b43a
Update code from upstream repository https://github.com/lowRISC/opentitan to revision ca950b43a0e9ef5013b8e2e5de765bc34fb59b74 Two updates to the Ibex code were required: * Adjust the prim_secded port names to match the changes in OpenTitan. * Replace `has_ral` in `ibex_icache_env_cfg.sv` and `ibex_icache_base_test.sv` with its newer equivalent, matching https://github.com/lowRISC/opentitan/pull/5932 and the additional updates in https://github.com/lowRISC/opentitan/pull/5951. Upstream changes include: * [prim_secded] Use _i/_o suffix for port names (Philipp Wagner) * [tl,dv] Allow bits to be set in responses regardless of mask (Rupert Swarbrick) * [push_pull agent] Driver code refactor (Srikrishna Iyer) * [dv/dvsim] Group failures per test in buckets (Guillermo Maturana) * [dv/uvmdvgen] Flag error for paths in block name (Guillermo Maturana) * [prim_fifo_async] Style fixes (Philipp Wagner) * Remove non-ASCII characters from SV code and meson.build (Rupert Swarbrick) * [dv/spi_device] Fix spi_device_csr_wr_with_rand_reset timeout issue (Cindy Chen) * [otp] Update to match latest foundry wrapper (Timothy Chen) * [flash] update to match latest foundry wrapper (Timothy Chen) * [top] Latest ast integration (Timothy Chen) * [lint] Strengthen Verible lint check to 100-character lines (Rupert Swarbrick) * [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo (Martin Lueker-Boden) * [dv/otp_ctrl] Add coverage exclusions (Cindy Chen) * [dv/dvsim] Add "^Error:" as a run fail pattern. (Guillermo Maturana) * [dvsim] Fix column bug in DV summary report (Srikrishna Iyer) * [dvsim] Fix testplan test counts (Srikrishna Iyer) * [dvsim] Fix lowRISC/opentitan#6061 (Srikrishna Iyer) * [prim_clock_div] Update waiver (Michael Schaffner) * [fpv] dvsim script error (Cindy Chen) * [prim_otp] Update interface (Michael Schaffner) * [dvsim] update edacloudlauncher imports (Udi Jonnalagadda) * [dv/doc] Minor fix on dv_doc (Cindy Chen) * [dvsim] Scheduler updates - max_parallel, max_poll (Srikrishna Iyer) * [dvsim] Set `Deploy.job_name` more robustly (Srikrishna Iyer) * [prim] Make SECDED prim generation deterministic (Rupert Swarbrick) * [tool, xcel] Support dumpping the array of struct in shm/vcd (Tung Hoang) * [dv/otp_ctrl] OTP_CTRL DV doc (Cindy Chen) * [dv/dv_macros] Fix DV_PRINT_ARR_CONTENTS (Guillermo Maturana) * [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner) * [prim_usb_diff] Minor lint fix (Michael Schaffner) * [prim_clock_div] Update waiver file (Michael Schaffner) * [top] change prim_generic usage into prim (Timothy Chen) * [formal/conn] Support dvsim to publish regression result summary (Cindy Chen) * Add formatting changes from allow list (Rafal Kapuscik) * [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin Vogel) * [prim] Add Width parameter to buffer primitives (Pirmin Vogel) * [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin Vogel) * [prim] Remove temporary workaround in parameter list related to primgen (Pirmin Vogel) * [dv/dvsim] Provides more context on some failures. (Guillermo Maturana) * [dvsim] Fix local run error. (Eunchan Kim) * [dv] Support multi-ral (part 4) (Weicai Yang) * [dv/dvsim] Adds failure bucketizer for triage. (Guillermo Maturana) * [lint/docs] Update ascentlint dvsim command in readme (Michael Schaffner) * [top] Various top level lint fixes (Timothy Chen) * [pinmux/padring] Wire up the pad attribute WARL behavior modules (Michael Schaffner) * [dv] Fix tl_error failure (Weicai Yang) * [pinout] Update flash test mode and voltage signals/pads (Michael Schaffner) * [pad_wrapper] Extend the generic and Xilinx pad wrapper models (Michael Schaffner) * [dv] Update scb for all blocks (Weicai Yang) * [dv] Support multi-ral (part 3) (Weicai Yang) * [prim_arbiter,lint] Tell Verilator to split variables for scheduling (Rupert Swarbrick) * [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin Vogel) * [dvsim] Scratch root default to $REPO_TOP/scratch (Srikrishna Iyer) * [dv] Update `process_tl_access` args for all blocks (Weicai Yang) * [dv] Support multi-ral (part 2) (Weicai Yang) * [formal] Clean up some formal warnings (Cindy Chen) * [topgen] Rework pinmux datastructure and templatize tops (Michael Schaffner) * [otp_ctrl] Several small lint fixes (Michael Schaffner) * [prim_fifo_async] Make async FIFO output zero when empty (Noah Moroze) * [flash] Improve flash ECC handling based on transasction attribute (Timothy Chen) * [dv] Remove toggle coverage excl for a_user/d_user (Weicai Yang) * [dvsim] Fix remaining comments from lowRISC/opentitan#5876 (Srikrishna Iyer) * [dv] Support multi-ral (part 1) (Weicai Yang) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Rupert Swarbrick
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8d37af2751 |
Update google_riscv-dv to google/riscv-dv@59dcd8c
Update code from upstream repository https://github.com/google/riscv- dv to revision 59dcd8c813484eb6dcca67e7e36089fe772b9cc8 * Update scripts for Metrics CI regression: bug fixes, change ISS to spike in CI regression (Aimee Sutton) * Add illegal and load store instruction (aneels3) * Avoid generating hint instruction when RV32C is turned off (google/riscv-dv#787) (taoliug) * Fix illegal opcode issue in the cov_test (google/riscv-dv#786) (taoliug) * [questa] Remove -access=rwc from vlog command line arguments (Rupert Swarbrick) * [ci] temporarily disable CI flow (Udi Jonnalagadda) * fix issue with rcs for num_of_harts (aneels3) * fix multi-hart label issue (aneels3) * add multi_hart test (ishita71) * Fix minor issues (aneels3) * Add riscv_signature_pkg (aneels3) * add gen_signature_handshake (ishita71) * Add gen_interrupt_vector_table (aneels3) * Remove the unnecessary lines (Anil Sharma) * fix issue with riscv_rand_instr_test (aneels3) * Add multiprocessing code block (aneels3) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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7d61def943 |
Update lowrisc_ip to lowRISC/opentitan@f29a0f7a7
Update code from upstream repository https://github.com/lowRISC/opentitan to revision f29a0f7a7115e03fba734b1c00691c253aceb07e. The list of OpenTitan changes that are merged in appears at the bottom of the commit. There are some manual changes needed to adapt the code to work with these changes. - The ICache monitors need some extra types to adapt to the (rather odd) data model that the OpenTitan dv_lib code now uses, where a monitor needs to know an agent's associated sequence type. - Verilator simulations now use MemArea slightly differently OpenTitan changes: * [dv] Allow monitor items to have different types from sequence items (Rupert Swarbrick) * [dvsim] Fix primary_cfg handling (Srikrishna Iyer) * [dvsim] Deal with non unicode chars in log files (Srikrishna Iyer) * [dvsim] Added common build fail patterns (Srikrishna Iyer) * [dvsim] Minot cleanup to the lint flow (Srikrishna Iyer) * [dvsim] Minor cleanups to to formal flow (Srikrishna Iyer) * [dvsim] Fixes to UNR and cov analysis flows (Srikrishna Iyer) * [dvsim] Very minor cleanup of Deploy class (Srikrishna Iyer) * [dvsim] LsfLauncher report early errors as F (Srikrishna Iyer) * [dvsim] Minor fix in clean_odirs function (Srikrishna Iyer) * [chip dv] Set +sw_images as comma-separated list (Srikrishna Iyer) * [flash_ctrl] Split tl intefaces for flash_ctrl and prim_flash_cfg (Timothy Chen) * [keymgr] Fix input value checks (Timothy Chen) * [formal/script] Update generic formal flow naming from `fpv` to `formal` (Cindy Chen) * [top, prim] Address wmask and data width mismatch issue (Timothy Chen) * [dvsim] Add GUI mode for running simulations (Srikrishna Iyer) * [dv] Fix reg backdoor (Weicai Yang) * [dpi] Make an "ECC32" flavour of MemArea (Rupert Swarbrick) * [uvmdvgen] Fix has_interrupts in env_cfg (Cindy Chen) * [dvsim] Keep dependencies list (Srikrishna Iyer) * [prim_prince] Reverse the k0||k1 mapping to match with the paper (Michael Schaffner) * [dvsim] Fix printing of last 10 lines (Srikrishna Iyer) * [primgen] Minor fix to enable types with underscores (Michael Schaffner) * [dvsim] Prevent command echo suppression (Srikrishna Iyer) * [dvsim] Spot fixes for LSF and internal launcher (Srikrishna Iyer) * [sva] csr assertion dependency update (Cindy Chen) * [memutil] Change DpiMemUtil so that it no longer owns MemAreas (Rupert Swarbrick) * [memutil] Factor out MemArea as a class (Rupert Swarbrick) * [prim] Split out PRESENT and PRINCE support from prim:all (Rupert Swarbrick) * [fpv/otp_ctrl] Disable assertions due to lc_esc_en (Cindy Chen) * [prim_prince] Annotate some arrays to avoid UNOPTFLAT warnings (Rupert Swarbrick) * [top] Hook up latest ast ports and complete a few other integration (Timothy Chen) * Eliminate `#pragma once` in favor of include guards (Chris Frantz) * [sw,dv] Update headers to pass fix_include_guards.py (Alex Bradbury) * [xbar/dv] Fix assertion error due to short reset (Weicai Yang) * [sram] Add memory initialization (Timothy Chen) * [uvmdvgen] Update links in checklist template (Philipp Wagner) * [dv/uvmdvgen] Add comment for testplan (Cindy Chen) * [dv/top_earlgrey] chip csr_aliasing timeout (Cindy Chen) * [dvsim] Cosmetic updates to launcher methods (Srikrishna Iyer) * [dv] Update csr_wr to support field write (Weicai Yang) * [dv/common] Fix regression warnings (Cindy Chen) * [dv] Get blocks with multiple device interfaces working with chip DV (Rupert Swarbrick) * [doc] Use relative links in Hjson-related shortcodes (Philipp Wagner) * [dvsim] minor enhancement to clean_odir (Srikrishna Iyer) * [dvsim] Statically display jobs' status (Srikrishna Iyer) * [dvsim] Do weighted scheduling of jobs (Srikrishna Iyer) * [dvsim] Schedule jobs by dependency (Srikrishna Iyer) * [dv] Xcelium UNR typo (Srikrishna Iyer) * [dvsim] Implement LsfLauncher (Srikrishna Iyer) * [dv/chip] solve same_csr_outstanding_timeout (Cindy Chen) * [dv] make dv_base_agent work for high-level agent (Weicai Yang) * [tools/dv] added UNR flow for xcelium (Rasmus Madsen) * [prim] Split prim:subreg out of prim:all (Rupert Swarbrick) * [prim] Split prim_alert_* out of prim:all (Rupert Swarbrick) * [prim] Split out fifos into a prim_fifo core (Rupert Swarbrick) * [prim] Split out arbiters into a prim_arbiter core (Rupert Swarbrick) * [prim] Make prim:flop_2sync depend on prim:flop (Rupert Swarbrick) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Tom Roberts
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2c75c2b2ec |
Update lowrisc_ip to lowRISC/opentitan@1ae03937f
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 1ae03937f0bb4b146bb6e736bccb4821bfda556b * [prim/fifo_async] Add assertions on pointers (Tom Roberts) * [prim/fifo_async] Add support for Depth <= 2 (Tom Roberts) * [prim/fifo_async] Code tidy-up (Tom Roberts) * [top / ast] Continued ast integration (Timothy Chen) * [dvsim] Use bash when running make underneath (Srikrishna Iyer) * [prim] Increase maximum width for prim_util_memload to 312 (Greg Chadwick) * [sram_ctrl] Fix potential back-to-back partial write bug (Michael Schaffner) * [dvsim] Fix for lowRISC/opentitan#5527 (Srikrishna Iyer) * [lint] Waive Verilator UNUSED warnings for packages (Rupert Swarbrick) * [uvmdvgen] Update DV doc path and terminology (Srikrishna Iyer) * [clkmgr] Fix dft issues (Timothy Chen) * [util] add `dec` types to prim_secded_pkg (Udi Jonnalagadda) * [util] minor updates to secded_gen (Udi Jonnalagadda) * [lint] Fix a bunch of lint warnings related to long lines (>100 chars) (Michael Schaffner) * [dv] Update common intr_test seq (Weicai Yang) * [util] Slight refactor of secded_gen.py (Timothy Chen) * [tlul] Add memory transmission integrity checks (Timothy Chen) * [dvsim] Move clean_odirs to `util.py` (Srikrishna Iyer) * [dvsim] Split Deploy into Deploy and Launcher (Srikrishna Iyer) * [dvsim] Add utils.TS_FORMAT* vars (Srikrishna Iyer) * [dv/lock_reg] Update IPs to adopt the lock_reg changes (Cindy Chen) * [dv/enable_regs] Support enable registers have more than one field (Cindy Chen) * [dv/base_reg] use m_field instead of accessing field (Cindy Chen) * [dv/sram] add SRAM scrambling model for DV (Udi Jonnalagadda) * [dv/tools] Updated Coverage flow for xcelium (Rasmus Madsen) Signed-off-by: Tom Roberts <tomroberts@lowrisc.org> |
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Tom Roberts
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5ef18f0b78 |
Update lowrisc_ip to lowRISC/opentitan@6cc5c164b
NOTE this commit includes various changes to align the Ibex repo with changes upstream in OT! Update code from upstream repository https://github.com/lowRISC/opentitan to revision 6cc5c164ba96d339f06cbcede0d17d2c96ce3c05 * [dv] Add SV_FCOV_SVA back (Srikrishna Iyer) * [DV][FCOV] Minor updates to lowRISC/opentitan#5414 (Srikrishna Iyer) * [dvsim] Fix --cov + --build|run-only bugs (Srikrishna Iyer) * [lint] Waivers for rv_core_ibex lint (Greg Chadwick) * [lint] Allow one branch in unique case (Greg Chadwick) * [dv/macros] Add fcov macros from Ibex (Tom Roberts) * [dvsim/verilator] Fix pre-build cmd failure when hw/foundry is absent (Michael Schaffner) * [verilator/otp] Enable OTP preloading in verilator (Michael Schaffner) * [dvsim] Use builtins wherever possible (Srikrishna Iyer) * [prim] Avoid an apparent combinatorial loop in prim_secded_*_dec.sv (Rupert Swarbrick) * [dv/shadow_reg] Fix aes shadow reg error (Cindy Chen) * [lint] Remove comportable waivers from non-comportable IPs (Michael Schaffner) * [dv] Fix VPD dumping (Srikrishna Iyer) * [prim] Waive Verilator lint warning in prim_lfsr.sv (Pirmin Vogel) * [dv] Hard code various dv connections until full hook-up (Timothy Chen) * [tlul] Add payload checker and generator on device side only. (Timothy Chen) * [prim_packer] Silence verilator width warnings (Rupert Swarbrick) * [dvsim] lint fixes to FlowCfg (Srikrishna Iyer) * [dvsim] Minor improvement to FlowCfg (Srikrishna Iyer) * [dvsim] lint fixes to Scheduler (Srikrishna Iyer) * [dvsim] Very small update to Timer. (Srikrishna Iyer) * [lint] Update Verible lint parser to detect Verible syntax errors (Michael Schaffner) * [lint] Spot errors in the lint flow that we weren't expecting (Rupert Swarbrick) * [lint] Remove Fusesoc-related message waivers (Michael Schaffner) * [top / rst] Adjust the way rst_ni is used in design (Timothy Chen) * [dvsim/syn] Update parsing script and area reporting (Michael Schaffner) * [dv/regwen] update REGWEN conventions (Cindy Chen) * [dv/tools] Bug fix to common.tcl tb_top section. (Eitan Shapira) * [dv] Fix stress_all with reset (Weicai Yang) * [prim] Add a new slow to fast clock synchronizer (Tom Roberts) * [prim] Minor lint fix (Tom Roberts) * [tlul] Add instruction type to tlul (Timothy Chen) * [top] Ast updates (Timothy Chen) * [lint] Increase threshold for max number of bits in an array (Michael Schaffner) * [dv] add dv_base_reg_pkg to env_pkg template (Udi Jonnalagadda) * [dv/verilator] Ignore foundry dir (Srikrishna Iyer) * [dv] Provide license diagnostic info for VCS (Srikrishna Iyer) * [prim/otp_ctrl] Fix ECC correctable bug in generic OTP wrapper (Michael Schaffner) * [prim_ram_1p_scr] Make parity and diffusion layer settings more flexible (Michael Schaffner) * [prim] fix flash sram adapter use for configuration space (Timothy Chen) * [dv] Make CSR fields randomizable by default. (Srikrishna Iyer) * [dv/prim] minor updates (Udi Jonnalagadda) * [top] Minor lint fixes (Timothy Chen) * [prim_flash] Flash port alignments (Michael Schaffner) * [prim_util_pkg] Fix DC warning in _clog2() (Philipp Wagner) * Add missing full_o output signal of prim_fifo_sync (Philipp Wagner) * [dv] Gracefully kill simulation (Srikrishna Iyer) * [dv] Minor updates to prim tbs (Srikrishna Iyer) * [flash / top] Minor edits based on reviews (Timothy Chen) * [flash_ctrl / top] Various functional updates to flash (Timothy Chen) * [dv/otp_ctrl] regwen sequence (Cindy Chen) * [prim] Wire up full_o sync fifo output port in prim_sram_arbiter (Rupert Swarbrick) * [dvsim] Generate FUSESOC_IGNORE at top of scratch root (Rupert Swarbrick) * Revert "[lint] Remove Fusesoc-related message waivers" (Michael Schaffner) * Revert "[lint] Rename tool warnings to flow warnings and reduce their severity" (Michael Schaffner) * Revert "[lint] Provision syntax error filter for Verible lint" (Michael Schaffner) * [prim] Update fifo behavior during reset (Timothy Chen) * [dv] Move cip related macros to cip_macros (Weicai Yang) * [dv/dvsim] Fix when next_item does not have dependency (Cindy Chen) * [prim_packer_fifo/rtl] reset to disable output controls (Mark Branstad) * [lint] Provision syntax error filter for Verible lint (Michael Schaffner) * [lint] Rename tool warnings to flow warnings and reduce their severity (Michael Schaffner) * [lint] Remove Fusesoc-related message waivers (Michael Schaffner) * [dv/dvsim] collect coverage in scheduler (Cindy Chen) * [dvsim] Fix Syn class (Michael Schaffner) * [dv/shadow_reg] move get_shadow_regs function to dv_base_ral_block (Cindy Chen) * [lc_ctrl] Switch ECC to standard Hamming code (Michael Schaffner) * [prim_ram_*p_adv/prim_otp] Add option to use standard Hamming ECC (Michael Schaffner) * [secded_gen] Fix template bug that results in lint error (Michael Schaffner) * [prim/fifo_async] Disallow non-power-of-two depths (Tom Roberts) * [dv/alert] update shadow_reg alert naming in DV (Cindy Chen) * [dv] Align csr::reset_asserted to actual reset pin (Weicai Yang) * [prim_secded*_fpv] Generate FPV testbenches (Michael Schaffner) * [prim_secded*] Regenerate all SECDED primitives (Michael Schaffner) * [secded_gen] Add ability to generate FPV TB's and correct Hamming code (Michael Schaffner) * [dvsim] Run cov_merge / cov_report as part of the main set of jobs (Rupert Swarbrick) * [dvsim] Get rid of Deploy's static dispatch_counter (Rupert Swarbrick) * [dvsim] Make the scheduling logic per-target (Rupert Swarbrick) * [dvsim] Remove "status" from Deploy items (Rupert Swarbrick) * [dvsim] Create jobs with dependencies instead of sub-jobs (Rupert Swarbrick) * [dvsim] Simplify SimCfg._gen_results (Rupert Swarbrick) * [dvsim] Factor deploy method out of Deploy object (Rupert Swarbrick) * [dvsim] Move time tracking into its own class in Deploy.py (Rupert Swarbrick) * [dvsim] Fix printing of Deploy objects (Rupert Swarbrick) * [dv] make dv_macros.svh more UVM_agnostic (Srikrishna Iyer) * [dv/prim] reduce smoke test iterations (Udi Jonnalagadda) * [dv/hmac] reduce runtime for sha_vector test in smoke regression (Cindy Chen) * [DV] Enable cov comp creation iff cov is enabled (Srikrishna Iyer) * [prim_alert] Fix xcelium compile error (Cindy Chen) * [alert_rxtx/fpv] Update alert sender FPV testbenches (Michael Schaffner) * [alert_rxtx] Add option to latch fatal alert in alert sender (Michael Schaffner) * [kmac/dv] KMAC smoke test (Udi Jonnalagadda) * [dv/str_utils_pkg] add byte_to_str function (Udi Jonnalagadda) * [prim] - Add new prim_lc_dec (Jacob Levy) * [util] Move design-related helper scripts to util/design (Michael Schaffner) * [prim-flash] Add missing deps (Srikrishna Iyer) * [dv] Define SIMULATION during DV sims (Michael Schaffner) * [dv] Fix a typo in tb.sv.tpl (Weicai Yang) * Cleanup: Remove executable bits from source files (Philipp Wagner) * [dv] Use separate clock for EDN (Weicai Yang) * [dv] Add macro DV_EDN_IF_CONNECT to simplify EDN connect in TB (Weicai Yang) * [dv] Fix typo in clk_rst_if (Weicai Yang) Signed-off-by: Tom Roberts <tomroberts@lowrisc.org> |
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Tom Roberts
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6e617c4097 |
[vendor] Remove fcov patch from dv_utils
This code is now upstream in the source repository. Also amend dv_utils patch to apply cleanly. Signed-off-by: Tom Roberts <tomroberts@lowrisc.org> |
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Greg Chadwick
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0cb2afffa9 |
Update google_riscv-dv to google/riscv-dv@0b62525
Update code from upstream repository https://github.com/google/riscv- dv to revision 0b625258549e733082c12e5dc749f05aefb07d5a * Add a knob to use rounding mode from the instruction (google/riscv- dv#767) (taoliug) * Add rounding mode support for floating point arithmetic instructions (google/riscv-dv#766) (taoliug) * Fix syntax issue (google/riscv-dv#765) (taoliug) * Add riscv_amo_instr (aneels3) * convert string to enum type (ishita71) * Remove unintended errors in the coverage flow (google/riscv-dv#757) (taoliug) * Fix c_test handling in the YAML testlist (google/riscv-dv#756) (taoliug) * Add support for new Spike trace format (google/riscv-dv#755) (Daniel Bates) * Fix google/riscv-dv#751 for floating point coverage (Weicai Yang) * Fix issues with implemented TODO's (aneels3) * fix randomize_gpr (aneels3) * Add file riscv_b_instr.py (ishita71) * add std_randomize todo (pvipsyash) * Add todo for floating_point test (ShraddhaDevaiya) * Add scripts to integrate with Metrics regression platform (Aimee Sutton) Includes a fix to dv/uvm/core_ibex/sim.py to use `asm_test` rather than `asm_tests` due to changes in RISCV-DV Signed-off-by: Greg Chadwick <gac@lowrisc.org> |
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Greg Chadwick
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860b085e25 |
[dv] Add RISCV-DV patch to fix csr_test
The assembly for the CSR test is generated by a script from RISCV-DV. A .org directive is required to put the generated code at the correct start address for the instantiated Ibex core. |
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Greg Chadwick
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d717e2385e |
Update lowrisc_ip to lowRISC/opentitan@7aa5c2b89
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7aa5c2b890fa5d4e3d0b43e0f5e561cb7743a01d * [flash] updated flash wrapper md file (Dana Agur) * [flash / top / ast] functional updates (Timothy Chen) * [ralgen, dv] Associated changes to ralgen (Srikrishna Iyer) * [prim_sync_reqack_data] Fix SVA checking DST-to-SRC data stability (Pirmin Vogel) * [dv/keymgr] temp disable alert checking in scb (Cindy Chen) * [dvsim] Fix a wrong path in print message (Weicai Yang) * [prim] Teach verilator to recognise a clock gate (Rupert Swarbrick) * [prim_lc_sync] Add AsyncOn parameter to enable/disable the sync flops (Michael Schaffner) * [clkmgr / top] Add clock divider step down to support lc_ctrl transition (Timothy Chen) * [prim_sync_reqack] Use NRZ protocol internally for increased throughput (Pirmin Vogel) * [prim] correct interface documentation. (Timothy Chen) * [flash_ctrl] Add tlul configuration interface to prim_flash (Timothy Chen) * [flash_ctrl] Use hamming code for 64b ECC (Timothy Chen) * [prim/edn] Fix lint error (width mismatch) (Eunchan Kim) Signed-off-by: Greg Chadwick <gac@lowrisc.org> |
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Greg Chadwick
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698cf93183 | [dv] Patch for fcov macros in dv_utils | ||
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Philipp Wagner
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b1daf9e44e |
Update lowrisc_ip to lowRISC/opentitan@c277e3a8
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7e131447da6d5f3044666a17974e15df44f0328b Updates to Ibex code to match this import: * Include str_utils in the imported code. * List new source files in dv/uvm/core_ibex/ibex_dv.f * Update patches to resolve merge conflicts. * Update tb_cs_registers.cc and ibex_riscv_compliance.cc to match the new return code of simctrl.Exec(). Imported updates: * Do not require pyyaml >= 5.1 (Philipp Wagner) * [prim_edn_req] Forward fips signal to consumer (Pirmin Vogel) * [prim_edn_req] Use prim_sync_reqack_data primitive (Pirmin Vogel) * [prim_edn_req] De-assert EDN request if packer FIFO has data available (Pirmin Vogel) * [cleanup] Mass replace tabs with spaces (Srikrishna Iyer) * [lc_ctrl] Add script to generate the LC state based on the ECC poly (Michael Schaffner) * [dvsim] Use list for rsync command (Eunchan Kim) * [verilator] Only control the reset line when necessary (Rupert Swarbrick) * [dv/csr_utils] Add debug msg for UVM_NOT_OK err (Cindy Chen) * [dvsim] Add exclude hidden files when needed (Eunchan Kim) * [prim_sync_reqack] Add variant with associated data and optional data reg (Pirmin Vogel) * [DV, Xcelium] Fix for lowRISC/opentitan#4690 (Srikrishna Iyer) * [dvsim] Remote copy update (Srikrishna Iyer) * [prim_edn_req] Add EDN sync and packer gadget primitive (Michael Schaffner) * [prim] Add hamming code as ECC option (Timothy Chen) * [DV] Cleanup lint warnings with Verible lint (¨Srikrishna) * [prim_ram] Rearrange parity bit packing and fix wrong wmask settings (Michael Schaffner) * [lc_sync/lc_sender] Absorb flops within lc_sender (Michael Schaffner) * [prim_otp_pkg] Move prim interface constants into separate package (Michael Schaffner) * [sram_ctrl] Pull scr macro out of sram_ctrl (Michael Schaffner) * [top] Move alert handler to periphs and attach escalation clock to ibex (Michael Schaffner) * [prim_esc_rxtx/rv_core_ibex] Add default values and NMI synchronization (Michael Schaffner) * [dvsim] Fix regression publish result link with --remote switch (Cindy Chen) * [vendor/ibex] Remove duplicate check tool requirements files (Michael Schaffner) * [prim_ram_1p_scr] Fix sequencing bug in scrambling logic (Michael Schaffner) * [prim_ram*_adv] Qualify error output signals with rvalid (Michael Schaffner) * [dvsim] Fix purge not delete remote repo_top (Cindy Chen) * [lc/otp/alerts] Place size-only buffers on all multibit signals (Michael Schaffner) * [prim_buf] Add generic and Xilinx buffer primitive (Michael Schaffner) * [prim] Packer to add byte hint assertion (Eunchan Kim) * [dvsim] Logic to copy repo to scratch area (Srikrishna Iyer) * [dv/lc_ctrl] enable lc_ctrl alert_test (Cindy Chen) * [prim] documentation update for flash (Timothy Chen) * [flash_ctrl] Add additional interface support (Timothy Chen) * [dvsim] Fix publish report path (Weicai Yang) * [top_earlgrey] Instantiate LC controller in toplevel (Michael Schaffner) * [doc] Fix checklist items in V1 (Michael Schaffner) * [dv/csr_excl] Fix VCS warning (Cindy Chen) * [dv/doc] cleaned up checkist alignment (Rasmus Madsen) * [doc/dv] cleanup (Rasmus Madsen) * [dv/doc] updated dv_plan links to new location (Rasmus Madsen) * [dv/doc] changed testplan to dv_plan in markdown files (Rasmus Madsen) * [dv/doc] changed dv plan to dv doc (Rasmus Madsen) * Remove redundant ascentlint options (Olof Kindgren) * Add ascentlint default options for all cores depending on lint:common (Olof Kindgren) * [flash] documentation update (Timothy Chen) * [flash / top] Add info_sel to flash interface (Timothy Chen) * [otp] lci interface assertion related fix (Cindy Chen) * [dv/uvmdvgen] Add switch to auto-gen edn (Cindy Chen) * [util] Rejig how we load hjson configurations for dvsim.py (Rupert Swarbrick) * added changes required by sriyerg (Dawid Zimonczyk) * update riviera.hjson (Dawid Zimonczyk) * [flash_ctrl] Add high endurance region attribute (Timothy Chen) * Change VerilatorSimCtrl::Exec to handle --help properly (Rupert Swarbrick) * Simplify handling of exit_app in VerilatorSimCtrl::ParseCommandArgs (Rupert Swarbrick) * [sram_ctrl] Rtl lint fix (Michael Schaffner) * [keymgr] Add edn support (Timothy Chen) * [dv] Make width conversion explicit in dv_base_env_cfg::initialize (Rupert Swarbrick) * [dvsim] Allow dvsim.py to be run under Make (Rupert Swarbrick) * [dvsim[ rename revision_string to revision (Srikrishna Iyer) * [dvsim] Update log messages (Srikrishna Iyer) * [dvsim] fix for full verbosity (Srikrishna Iyer) * [dv] Fix Questa warning and remove unused var (Weicai Yang) * [dvsim] Add alias for --run-only (Weicai Yang) * [keymgr] Hook-up random compile time constants (Timothy Chen) * [dvsim] Add support for UVM_FULL over cmd line (Srikrishna Iyer) * [dv common] Enable DV macros in non-UVM components (Srikrishna Iyer) * [DVsim] Add support for Verilator (Srikrishna Iyer) * [DVSim] Fix how sw_images is treated (Srikrishna Iyer) * [DV common] Fixes in sim.mk for Verilator (Srikrishna Iyer) * [DV Common] Split DV test status reporting logic (Srikrishna Iyer) * [prim_arbiter_ppc] Fix lint error (Philipp Wagner) * [DV common] Factor `sim_tops` out of build_opts (Srikrishna Iyer) * [dvsim] run yapf to fix style (Weicai Yang) * [dv/common] VCS UNR flow (Weicai Yang) * [dv] Add get_max_offset function in dv_base_reg_block (Weicai Yang) * [otp_ctrl] Fix warnings from VCS (Cindy Chen) * [lint] Change unused_ waiver (Eunchan Kim) * [dv/alert_test] Add alert_test IP level automation test (Cindy Chen) * [DV] Update the was SW is built for DV (Srikrishna Iyer) * [dvsim] Replace `sw_test` with `sw_images` (Srikrishna Iyer) * [chip dv] Move sw build directory (Srikrishna Iyer) * [dv common] Update dv_utils to use str_utils_pkg (Srikrishna Iyer) * [DVSim] Method to add pre/post build/run steps (Srikrishna Iyer) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Rupert Swarbrick
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4852e307b7 |
Update lowrisc_ip to lowRISC/opentitan@e619fc60
This updates the vendored code from OpenTitan and fixes up patches as we go. The biggest change is that the support files that were in dv/data have moved to dv/tools/dvsim (with a couple of other internal renames). The icache test code also needs the corresponding path change and to rename its regression from "sanity" to "smoke" (the new name for the default regression). Update code from upstream repository https://github.com/lowRISC/opentitan to revision e619fc60c6b9c755043eba65a41dc47815612834 * [dv] Remove duplicated keys from common_sim_cfg.hjson (Rupert Swarbrick) * [dv] two small fix in dv (Cindy Chen) * [dv] Comment out example build modes from common_sim_cfg.hjson (Rupert Swarbrick) * [dv/keymgr] Cleanup some warnings in xcelium (Weicai Yang) * [lc_ctrl] Reuse an instance of the RISC-V dmi_jtag as the LC TAP (Michael Schaffner) * [otp_ctrl] Update LC types within OTP (Michael Schaffner) * [lc_ctrl] Add first cut implementation (Michael Schaffner) * [flash_ctrl] update prim flash interface (Timothy Chen) * [flash_ctrl] Add support for isolated flash partition (Timothy Chen) * [dv/common] update naming from sanity to smoke (Cindy Chen) * [prim] update naming from sanity to smoke (Cindy Chen) * [dv/base] add get_reg_by_name support in dv_base_reg_block (Cindy Chen) * [cov methodology] Functional coverage prototype (Srikrishna Iyer) * [dv] Fix tpyo (Weicai Yang) * [dv common] Wave dumping improvements / fix (Srikrishna Iyer) * [dv] Fix for `--run-only` switch (Srikrishna Iyer) * [prim_present] Add support for iterative full-round PRESENT (Michael Schaffner) * [dv] Fix VCS compile error (Weicai Yang) * [sparse-fsm-encode] Switch to Safe Rust Encoding (Sam Elliott) * [sparse-fsm-encode] Disallow Complementary Encodings (Sam Elliott) * [prim/util] Fix parameter type when using prefixes (Pirmin Vogel) * [keymgr/prim_lfsr] Correct minor errors in core files (Michael Schaffner) * [design checklist] avoid using word sanity (Cindy Chen) * [prim_lc_sync] Add two stage sync for life cycle control signals (Michael Schaffner) * [flash] update flash program to support ack / done / last (Timothy Chen) * [prim] update prim flash to have ack / done support (Timothy Chen) * Fix typo in testplan template (Rupert Swarbrick) * [dv] Fix license header for some cfg files (Weicai Yang) * [dv] Only check scoreboard from pre_abort if we were in run phase (Rupert Swarbrick) * [doc] Add lint requirements to V1 checklist (Cindy Chen) * [dv common] Minor enhancements to dv_reg_block (Srikrishna Iyer) * [dv] Fix library paths for dsim (Srikrishna Iyer) * [keymgr/dv] Update testbench (Weicai Yang) * [dv/common] Add DV_ALERT_IF_CONNECT macro (Weicai Yang) * [dv, common] Promote VCS warning to error (Srikrishna Iyer) * [prim] update clock_mux prim to avoid using BUFG (Timothy Chen) * [clkmgr] Add divider bypass during test mode (Timothy Chen) * [opt_ctrl] Change state_q assignment to ease debugging (Michael Schaffner) * [doc] Update D2 checklist and propagate updates to IPs (Michael Schaffner) * [dv/dvsim] Fix -c option compile error (Cindy Chen) * [dv] Tidy up use of get_normalized_addr (Rupert Swarbrick) * [fpv] Fix fusesoc dependecy issue (Cindy Chen) * [lint] Fix lint warning (Cindy Chen) * [dv/lint] Add new DV TB to lint batch script (Cindy Chen) * [fpv] Add lint checking to FPV tb (Cindy Chen) * [dvsim] Remove process_exports() from the code (Srikrishna Iyer) * [dvsim] Fix HJson bugs (Srikrishna Iyer) * [fpv] alert_rx/tx updates (Cindy Chen) * [prim] slicer lint fix (Eunchan Kim) * [prim] Packer to remove unused parameter. (Eunchan Kim) * [prim_lfsr] Update prim_lfsr and testbench to use correct perm width (Michael Schaffner) * [prim_lfsr] Add script to generate seed and perm constants (Michael Schaffner) * [dv/common] Upgrade some VCS warnings to errors (Weicai Yang) * [dvsim] Document and slightly improve subst_wildcards in utils.py (Rupert Swarbrick) * [csrng/dv] Initial dv environment (Steve Nelson) * [sparse-fsm-encode] Update template to prevent JG compile error (Michael Schaffner) * Gracefully shut down Verilator when software test fails (Philipp Wagner) * [otp] fix FPV compile error (Cindy Chen) * [dvsim] Kill subprocesses more gracefully (Rupert Swarbrick) * [prim] Fix Verilator lint warnings (Pirmin Vogel) * [memutil] Allocate the right number of bytes in StagedMem::GetFlat() (Rupert Swarbrick) * [memutil] Load ELF files via a staging area (Rupert Swarbrick) * [memutil] Add iterator and merging insertion interfaces to RangedMap (Rupert Swarbrick) * [memutil] Factor out "ranged map" implementation from dpi_memutil (Rupert Swarbrick) * [alert_handler] update alert hander ports (Timothy Chen) * [otp_ctrl] Update OTP output data mapping (Michael Schaffner) * [otp_ctrl] Split partition metadata into separate package (Michael Schaffner) * [prim_otp] Add TL-UL regfile for testing (sim only) (Michael Schaffner) * [memutil] Split out the non-verilator part of verilator_memutil (Rupert Swarbrick) * [dv/common] Update DV_CHECK_* macros (Weicai Yang) * [dv/common] Fix testplan path (Weicai Yang) * [prim_assert] Fixed non-UVM part of `ASSERT_ERROR (Srikrishna Iyer) * [otp_ctrl] Simplify and consolidate OTP error codes (Michael Schaffner) * [kmac] Fix critical syntax errors. (Eunchan Kim) * [dv/common] Move testplan from tools directory to data (Weicai Yang) * [dvsim] Rename verbosity wildcards to something more informative (Rupert Swarbrick) * [dv/lfsr] Update prim_lfsr_sim_cfg.hjson and add coverage (Udi Jonnalagadda) * [dv common] Added string check macros (Srikrishna Iyer) * [rtl] Use platform-agnostic log macros prim_assert (Srikrishna Iyer) * [dv] Minor fixups to dv_Utils_pkg (Srikrishna Iyer) * [dv] Fix platform-agnostic log macros (Srikrishna Iyer) * [checklist] Upgrade wording for D1 milestone (Scott Johnson) * [entropy_src/rtl] fix for dv sanity test (Mark Branstad) * [lint] Add option to bail out on first invalid Tcl cmd (Michael Schaffner) * [sram_ctrl] Add first cut implementation (Michael Schaffner) * [prim] Fix AscentLint waiver that made the tool crash (Michael Schaffner) * [checklists] Clean up and align HW and SW checklists (Michael Schaffner) * [prim] Update signal name in lint waiver rule (Pirmin Vogel) * [flash_ctrl] Switch to new keyschedule in PRINCE (Michael Schaffner) * [lint] fix the waiver format (Eunchan Kim) * [dv] Waive lint warnings in dv_macros.svh (Srikrishna Iyer) * [dv common] Add platform-agnostic log macros (Srikrishna Iyer) * [util] Add Rust Enum Support to sparse-fsm-encode.py (Sam Elliott) * [util] Add C Enum Support to sparse-fsm-encode.py (Sam Elliott) * [sparse-fsm-encode] Expand error and help messages (Michael Schaffner) * [dv/common] TLUL agent function coverage (Weicai Yang) * [dv/shadow_reg] support alert handshake checking (Cindy Chen) * [prim_present/otp_ctrl] Add round index state IOs to primitive (Michael Schaffner) * [dv] Fix 2 regression failures (Weicai Yang) * [prim_multibit_sync] Add multibit synchronizer with consistency check (Michael Schaffner) * [prim] Fix Lint warning for prim_slicer (Eunchan Kim) * [prim_generic_otp] Add TL-UL test interface stub for DV (Michael Schaffner) * [doc] Improve documentation for common_ifs (Rupert Swarbrick) * [doc] Improve pins_if block diagram (Rupert Swarbrick) * [prim_prince/present] Remove TODOs (Michael Schaffner) * [dv/common] Change TL item content when it's not accepted (Weicai Yang) * [dv/uvmgen] update has_alerts (Cindy Chen) * [dv/common] Add run opt plusarg to enable file path in the log (Weicai Yang) * [prim] Add clock buffer primitive for Xilinx FPGAs (Pirmin Vogel) * [otp_ctrl] Provision power sequencing signals (Michael Schaffner) * [dv/common] Clean up old makefile flow (Weicai Yang) * [entropy_src/rtl] review round2 changes (Mark Branstad) * [otp_ctrl] Update all FSMs to use prim_flop for the state (Michael Schaffner) * [prim_xilinx_flop] Add a Xilinx version with keep attribute (Michael Schaffner) * [prim/util] Update sparse-fsm-encode and include FSM template (Michael Schaffner) * [DV macros] minor enhancement to `DV_SPINWAIT (Srikrishna Iyer) * [DV common] Add DV_ASSERT_CTRL macro (Srikrishna Iyer) * [DV common] Enhance `DV_CHECK_MEMBER_RANDOMIZE_*` (Srikrishna Iyer) * [otbn] Use relative scope names for OTBN scopes (Rupert Swarbrick) * [verilator simutil] Add support for relative scope names to SVScoped (Rupert Swarbrick) * [fpv/prim_packer] remove assumption (Cindy Chen) * [fpv/csr_assert] support all modules for CSR assert (Cindy Chen) * [memutil] Teach verilator_memutil to load multi-segment ELF files (Rupert Swarbrick) * [memutil] Simplify how we read ELF files in verilator_memutil.cc (Rupert Swarbrick) * [memutil] Add a "verbose" flag to detail memory loads (Rupert Swarbrick) * [memutil] Parse all arguments before loading anything (Rupert Swarbrick) * [memutil] Use override keyword, not virtual for overridden method (Rupert Swarbrick) * [memutil] Use exceptions to simplify error handling (Rupert Swarbrick) * [memutil] Store the width of memory areas in bytes, not bits (Rupert Swarbrick) * [memutil] Allow memory locations to have associated LMAs (Rupert Swarbrick) * [memutil] Improve type of ElfFileToBinary in verilator_memutil.cc (Rupert Swarbrick) * [verilator simutil] Move SVScoped class into dv/verilator/cpp (Rupert Swarbrick) * [memutil] Move static functions out of VerilatorMemUtil class (Rupert Swarbrick) * [memutil] Run clang-format on verilator_memutil.* (Rupert Swarbrick) * [dv:entropy_src] Initial rng_agent and integrated into entropy_src env (Steve Nelson) * [prim_ram_adv/fpv] fix assertion (Cindy Chen) * [prim_ram_1p_scr] Simplify nonce input and align to multiples of 64b (Michael Schaffner) * [fpv/csr_assert] add csr support for regwen (Cindy Chen) * [prim*] Various lint fixes in the prims (Michael Schaffner) * [prim] remove FPV related assertions (Eunchan Kim) * [prim_lfsr] Add option to supply custom output permutation (Michael Schaffner) * [dv/common] calculate addr map size in RAL (Weicai Yang) * [flash_ctrl] Add ECC to program / erase datapaths (Timothy Chen) * [otp_ctrl] First cut implementation of the OTP controller (Michael Schaffner) * Fix invalid read in verilator_memutil (Rupert Swarbrick) * [doc] Don't strip markdown headings from HW checklist (Philipp Wagner) * [site] Set lint title (Tobias Wölfel) * [dv/prim] add basic PRINCE testbench (Udi Jonnalagadda) * [flash_ctrl] Support the notion of a 'program-repair'. (Timothy Chen) * [prim/tlul] Various small lint fixes (Michael Schaffner) * [dv/uvmdvgen] update dvsim and remove Makefile (Cindy Chen) * [util] Add script for generating sparse FSM encodings (Michael Schaffner) * [prim] Add option to register output for interrupts (Timothy Chen) * [prim_otp] First cut implementation of FPGA emulation (Michael Schaffner) * [prim_ram_1p_adv] Add 16bit ECC mode (Michael Schaffner) * [chip dv] Fix for failing GPIO test (Srikrishna Iyer) * [RTl] Generic pad wrapper default behavior fix (Srikrishna Iyer) * [slicer] Select partial from bitstream (Eunchan Kim) * [util] Don't hack __repr__ in FlowCfg (Rupert Swarbrick) * [util] Fix lint in dvsim.py (Rupert Swarbrick) * [fpv/prim_packer] Add a FPV TB (Cindy Chen) * [Keccak] Keccak_f implementation (Eunchan Kim) * [dv/csr] add common task for csr_or_field_rd_check (Cindy Chen) * [keccak] Add valid signal to random value (Eunchan Kim) * [prim] Add primitive clock divider (Timothy Chen) * [dv/shadow_reg] update sequence for storage error (Cindy Chen) * [dv/lib] clear csr_outstanding_access after reset (Cindy Chen) * [sw] Ensure Headers are Correctly Ordered (Sam Elliott) * [dv] Fix csr_rd check during reset (Weicai Yang) * Adding the first update to coverage methodology (Rasmus Madsen) * [dv] TL agent supports no clock reset (Weicai Yang) * [tlul/dv] Update test plan for tl errors (Weicai Yang) * [fpv/alert] update namings for FPV tb (Cindy Chen) * [keccak] Masked/Unmasked Keccak single round (Eunchan Kim) * [lint/prim*] Waive STAR_PORT_CONN_USE errors in generated prims (Michael Schaffner) * [prim_usb_diff_rx] Carry over wrapper for USB diff receiver (Michael Schaffner) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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623402cf6f |
Vendor in hw/dv/{data,tools} from OpenTitan
This gets the rest of the support code needed for dvsim (which we currently duplicate). The patch: - adds the relevant directories to the vendoring file - adds a patch to rewrite some OpenTitan-specific bits - adds a "common_project_cfg.hjson" - re-runs the vendoring tool This patch won't yet change how DV code runs; we also need to redirect a couple of paths and delete dv/uvm/data for that. This will happen in the next patch. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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690f8af65e |
Update paths for vendored DV code
This commit amends some paths in the vendoring hjson file (and updates config files to use things at the new paths). Finally it re-runs the vendoring tool: Update code from upstream repository https://github.com/lowRISC/opentitan to revision 92e9242424c72c59008e267dd3779e2af5ec8e83 which just ends up with a load of file renames. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Udi Jonnalagadda
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c10a050526 |
Update google_riscv-dv to google/riscv-dv@3da32bb
Update code from upstream repository https://github.com/google/riscv- dv to revision 3da32bbf6080d3bf252a7f71c5e3a32ea4924e49 * fix location of custom CSR setup (google/riscv-dv#747) (udinator) Signed-off-by: Udi Jonnalagadda <udij@google.com> |
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Udi Jonnalagadda
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7aeb2072aa |
Update google_riscv-dv to google/riscv-dv@3467c37
Update code from upstream repository https://github.com/google/riscv- dv to revision 3467c3777cb428b2e30b30b7f895a8fd73873d4f * add VCS compile option for unicode (Udi Jonnalagadda) * Add missing license header (aneels3) * [Docs] Fix broken links and typos (db434) * Add support for RV32D (ishita71) * Fix google/riscv-dv#733 (aneels3) * Fix Spike Issue (aneels3) * add riscv_reg and riscv_privil_reg (pvipsyash) * fix target issue for foating point (pvipsyash) * add rv32fc target (pvipsyash) * add riscv_floating_point_instr (pvipsyash) * Add defines for floating point instructions (ShraddhaDevaiya) Signed-off-by: Udi Jonnalagadda <udij@google.com> |
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Udi Jonnalagadda
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9b656a0a2c |
Update google_riscv-dv to google/riscv-dv@39797b2
Update code from upstream repository https://github.com/google/riscv- dv to revision 39797b2f07784e775149a4f05c90fee2427124e5 * coverage flow updates (Udi Jonnalagadda) * Update src/riscv_debug_rom_gen.sv (Tom Roberts) * debug_rom_gen: Fix return address issue (Tom Roberts) * Add sfence.vma after PTE process (google/riscv-dv#731) (taoliug) * generate gen_config data in tabular format (aneels3) * Fix coverage issue for ml target (google/riscv-dv#729) (taoliug) * Fix index offset constraint conflict (google/riscv-dv#728) (taoliug) * Fix rcs import and create_instr function (aneels3) * Fix setup_misa and formatting issue (aneels3) * Fix SPIKE ISSUE google/riscv-dv#722 (aneels3) * Fix coverage issue (aneels3) * fix google/riscv-dv#725 (Udi Jonnalagadda) * Fix formatting and linting issue (aneels3) * Add function setup_misa (ShraddhaDevaiya) * Fix gen_trap_handler_section (aneels3) * Add constraint (ShraddhaDevaiya) * Fixed push_gpr_to_kernel def (Saurabh Singh) * Add ic file to the target dir (aneels3) * Fix timeout issue (aneels3) * add mtvec constraint (pvipsyash) * Fix create_instr issue (aneels3) * Add function push_gpr_to_kernel (ishitapvips) * Fix invalid CSR test for RV64GCV target (google/riscv-dv#720) (taoliug) * Fix solve...before... on non-rand variables issue (google/riscv- dv#719) (taoliug) * Add rv32c instructions (aneels3) * Modify riscv_instr class fields (aneels3) * Fix import issue (aneels3) * Significantly improves performance of pyflow functional coverage (through changing the way that covergroups are instantiated & data are sampled) (Hodjat Asghari Esfeden) * fix jumps to `test_done` and `init_[m/s/u]_mode` (google/riscv- dv#710) (udinator) * Fix multi-harts program generation with PMP enabled (google/riscv- dv#716) (taoliug) * Fix google/riscv-dv#681 (google/riscv-dv#715) (taoliug) * Add initial support for rv32imc (aneels3) * resolve conflicts (aneels3) * add rv32imc core setting (pvipsyash) * changes for core settings (pvipsyash) * add riscv_compressed_instr (aneels3) * Convert code to be PEP8 compliant (Hodjat Asghari Esfeden) * Add riscv_data_page_gen (aneels3) * Integrates functional coverage side of pyflow into cov.py (google/riscv-dv#708) (Hodjat Asghari Esfeden) * Workaround of the SV compilation problem caused by assigning the const array variable with the empty concatenation. (google/riscv- dv#704) (Dariusz Stachańczyk) * Add rv32m and rv32c instr defines (ShraddhaDevaiya) * Fix logging issue along with other minor fixes (Hodjat Asghari Esfeden) * Add push_stack and pop_stack instr. (ShraddhaDevaiya) * Fix minor issues (aneels3) * Add a target for RV32IMC with SV32 address translation (google/riscv-dv#699) (taoliug) * Fixes a minot import issue (Hodjat Asghari Esfeden) * Fix LR/SC sequence issue (google/riscv-dv#698) (taoliug) * fix ebreak generation bug (google/riscv-dv#689) (udinator) * Update vector extension to v0.9 (google/riscv-dv#697) (taoliug) * Fixes a few issues in riscv_asm_program_gen and riscv_instr_gen_config (Hodjat Asghari Esfeden) * fix iterate over args dict (pvipsyash) * fix parse_args (pvipsyash) * fix cmdline argparse for directed stream (pvipsyash) * [pygen/riscv_instr_stream] Fix ebreak generation (Udi Jonnalagadda) * Fix flake8 related formatting (aneels3) * Add jal instr (aneels3) * Fixes for same rd for main instructions (Saurabh Singh) * Fixes to resolve label issue for directed class (Saurabh Singh) * Add constraint on jump_start (ShraddhaDevaiya) * Add Constraint for jump instructions. (ShraddhaDevaiya) * fix minor issue in directed_lib (pvipsyash) * Add riscv_jal_instr to directed_lib (pvipsyash) * Fix forward branch label compilation error (aneels3) Signed-off-by: Udi Jonnalagadda <udij@google.com> |
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Philipp Wagner
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f53ee9b09f |
Update google_riscv-dv to google/riscv-dv@2e52518
Update code from upstream repository https://github.com/google/riscv- dv to revision 2e5251846efb5fa42882a2b6b571ef8693e8cd60 * Remove f strings for Python 3.5-compatibility (Philipp Wagner) * Fix start-end pair mismatch in asm file (aneels3) * Fix AMO instruction constraint issue (google/riscv-dv#682) (taoliug) * - Adds support for the coverage report visualization (pyucis-viewer) - Adds CSR, opcode, rv32i_misc, and mepc_alignment covergroups (Hodjat Asghari Esfeden) * fix Todo of directed_lib (aneels3) * Added avail_regs_c constraint (ShraddhaDevaiya) * Fix factory method implementation (aneels3) * Add directed instr (aneels3) * fix label issue (aneels3) * fix randomization issue (aneels3) * Fix typo (aneels3) * add riscv_pseudo_instr (aneels3) * add value_plusargs functionality (pvipsyash) * add riscv_utils and fix minor issues (aneels3) * modify for directed scenario (pvipsyash) * Fix a minor issue with the instruction PC (Hodjat Asghari Esfeden) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Udi
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16ed993486 |
Update google_riscv-dv to google/riscv-dv@17d7984
Vendor in some updates to PMP test generation. Update code from upstream repository https://github.com/google/riscv- dv to revision 17d79847e376a591cb3dcaae7601c98b0e70e8ac * Update pygen/pygen_src/isa/riscv_cov_instr.py (Hodjat Asghari Esfeden) * Minor issues fixed in the functional coverage flow (Hodjat Asghari Esfeden) * fix pmp offset constraint (Udi Jonnalagadda) * Fix minor issues (aneels3) * - Adds riscv_instr_cover_group file with a few covergroups - Confirms riscv_instr_cov_test script is up and running fine - Initializes the registers to 0 during their first gpr_state access (for ovpsim output log) (Hodjat Asghari Esfeden) * update directed pmp sequence constraint (Udi Jonnalagadda) * remove unreachable if...else statement (Udi Jonnalagadda) * update post_process() (aneels3) * add ecall_handler (aneels3) * Fix post_process() issue (aneels3) * Fix typo in post_process (aneels3) * Completed riscv_cov_instr class (decoupled from riscv_instr_cov_test file) Added private _riscv_cov_instr module to manually retrieve format/category/group/imm_t based on the name of the instruction (Hodjat Asghari Esfeden) * add post_process() (aneels3) Signed-off-by: Udi <udij@google.com> |
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Rupert Swarbrick
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d71aaeee06 |
Update lowrisc_ip to lowRISC/opentitan@92e92424
The shortlog from the vendor tool's automated patch is reproduced at
the bottom of this commit message.
The automated commit is squashed with one to update how we depend on
bus parameters. Before, we had to provide an "Ibex top package". This
behaved the same as OpenTitan's "lowrisc:constants:top_pkg", but
avoided having to vendor in that file.
On the OpenTitan side, this has been tidied up with commit
d266c68 ("[dv] Update dv_utils sources to use bus_params_pkg"). This
changes the dependency of dv_utils to
"lowrisc:opentitan:bus_params_pkg". We still have to provide our
own (now called "lowrisc:ibex:bus_params_pkg") and need to patch the
dv_utils dependency, but this is a bit cleaner because dv_utils is
less likely to accidentally include dependencies on OpenTitan
internals.
On our side, we have to update the vendoring patch for dv_utils (and
change its name). We also need an equivalent patch for dv_lib. Then we
rename our hacky "Ibex top package" to "bus_params_pkg". The ICache DV
environment also needs patching to use the bus parameters properly.
Phew!
* [dv] Update prim_present cov opt (Srikrishna Iyer)
* [dv] Align VCS and Xcelium cov var names (Srikrishna Iyer)
* [dv] Split coverage for functional and auto tests (Srikrishna Iyer)
* [dvsim] Do builds smartly (Srikrishna Iyer)
* [syn] Carry over synthesis flow updates from bronze (Michael
Schaffner)
* [dvsim] Lint cleanup (Srikrishna Iyer)
* [dvsim] Allow testplan to be omitted (Srikrishna Iyer)
* [dvsim] Address lowRISC/opentitan#3071 comments (Srikrishna Iyer)
* [dvsim] lint cleanup (Srikrishna Iyer)
* [dvsim] Add support for second-level indirection (Srikrishna Iyer)
* [dvsim] Change cores-root to avoid conflicts with autogen'd core
files (Michael Schaffner)
* [dvsim] Update `tests` key behavior in regressions (Srikrishna Iyer)
* [lint] Minor update of ERROR patterns in parser script (Michael
Schaffner)
* [packer] Revise the implementation (Eunchan Kim)
* [flow] Remove lint makefile (Timothy Chen)
* [flows] Various updates to tools and documents to suppose top/ip
select (Timothy Chen)
* [dv/shadow_reg] shadow_reg update error (Cindy Chen)
* [rtl/alert] change the naming from _en_i to _req_i (Cindy Chen)
* [dvsim] Tidy up config file loading in FlowCfg.py (Rupert Swarbrick)
* [dvsim] Make it simpler to derive from FlowCfg (Rupert Swarbrick)
* [lint] Update warning/error exclusions in parser scripts (Michael
Schaffner)
* [dvsim] Fix for `--tool` override (Srikrishna Iyer)
* [dvsim] Bug fix in LintCfg.py (Srikrishna Iyer)
* [prim/dv] Integrate LFSR TB with dvsim (Udi Jonnalagadda)
* [uvmdvgen] Update template to reflect bind reorg (Srikrishna Iyer)
* [dv] remove prim_lfsr_bind (Srikrishna Iyer)
* [dv] Cleanup lint warnings in csr_utils_pkg (Srikrishna Iyer)
* [dv] Cleanup lint warnings in clk_rst_if (Srikrishna Iyer)
* [dvsim] Fix coverage dashboard link (Srikrishna Iyer)
* [prim] Rename prim_util_memload.sv to svh (Philipp Wagner)
* [lint/doc] Update linting readme to reflect recent updates (Michael
Schaffner)
* [lint] Remove legacy Makefile flow for linting tools (Michael
Schaffner)
* [dvsim/lint] Enable Verilator lint in Dvsim (Michael Schaffner)
* [prim_arbiter_fixed/fpv] Add generated FPV testbench (Michael
Schaffner)
* [prim_arbiter_fixed] This adds a fixed priority arbiter (Michael
Schaffner)
* [prim] Domain-Oriented Masking AND logic (Eunchan Kim)
* [dv] Update dv_utils sources to use bus_params_pkg (Srikrishna Iyer)
* [dv] Update mem_model to use bus-params_pkg (Srikrishna Iyer)
* [dv] Update dv_lib sources to use bus_params_pkg (Srikrishna Iyer)
* [uvmdvgen] Support for setting vendor name in VLNV (Srikrishna Iyer)
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Udi
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3ddc92a0fa |
Update google_riscv-dv to google/riscv-dv@61755c0
Update code from upstream repository https://github.com/google/riscv- dv to revision 61755c001bec0433fb69458f74d95476d2101cf3 * Adds new PMP directed sequence. (Udi Jonnalagadda) * Fix typo (aneels3) * Add gpr_c constraint (aneels3) * Corrections of a code formatting. (Dariusz Stachanczyk) * Modify asm, config and pkg files. (aneels3) * fix riscv_privil_reg compile error (google/riscv-dv#666) (udinator) * Added methods to the coverage test file (Hodjat Asghari Esfeden) * Constraints should contain only intergral types - fix added for a string variable used in nfields_c constraint. (Dariusz Stachanczyk) * Minor fixes on coverage test (Hodjat Asghari Esfeden) * fix pmpcfg csr definitions (Udi Jonnalagadda) * Pygen: minor fix (danghai) * Pre_sampling extension (Hodjat Asghari Esfeden) * Fix opcode in b_extension_c constraint (google/riscv-dv#659) (udinator) * Add vector AMO instruction support (google/riscv-dv#658) (taoliug) * Terminate when it cannot insert instruction (danghai) * Riscv_instr_cov added, riscv_instr_cov_test extended, comment applied (except for csv_dir) (Hodjat Asghari Esfeden) * Fix Indentation (aneels3) * fix imm constraint issue (aneels3) * fix typo in extend_imm() (aneels3) * Hodjat (Hodjat Asghari Esfeden) Signed-off-by: Udi <udij@google.com> |
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Udi
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216ba1a42d |
Update google_riscv-dv to google/riscv-dv@3cf691d
Update code from upstream repository https://github.com/google/riscv- dv to revision 3cf691dcb96f2cd72250690216b60f2b0c0ac804 * remove hardcoded CSR names (Udi Jonnalagadda) * initial custom CSR support (Udi Jonnalagadda) * Add support for segmented load/store instructions (google/riscv- dv#656) (taoliug) * fix post_randomize issue (aneels3) * add MAX_LMUL to rv32i config (google/riscv-dv#649) (udinator) * Ignore log and asm file (aneels3) * Add Command Line Support (aneels3) * support for command-line arguments (pvipsyash) * Reorder import statements (aneels3) * Modified function randomize_gpr in instr_stream file (ShraddhaDevaiya) * Updated riscv_instr_sequence file and modified other python files to get main block in asm file. (ShraddhaDevaiya) * Modify get_rand_instr() (aneels3) * added uvm_glob_to_re in uvm_re_match (Dawid Zimonczyk) * Aldec Riviera-PRO compiler command line arguments modified. (google/riscv-dv#638) (Dariusz Stachańczyk) * allow coverage compilation to be run on LSF (google/riscv-dv#637) (udinator) * Add CHIPS Alliance work group information to the README (google/riscv-dv#633) (taoliug) * Add indexed/strided vector load/store instrution stream (google/riscv-dv#632) (taoliug) * Add constraint for mtvec alignment in vectored interrupt mode (google/riscv-dv#631) (taoliug) * Add bitstring requirement to pygen/experimental README (google/riscv-dv#630) (taoliug) * Add unsupported load/store instruction filtering (google/riscv- dv#629) (taoliug) * Add different methods to initialize the vregs (google/riscv-dv#627) (Josep Sans) * Support a vetor instruction only mode (google/riscv-dv#626) (taoliug) * Add riscv_instr_stream.py file (aneels3) * Importing PyVSC module (google/riscv-dv#625) (Hodjat Asghari Esfeden) * update pygen_src files (google/riscv-dv#612) (BharathNR1030) * Fix typo (google/riscv-dv#624) (taoliug) * Fix B-ext instruction generation issue (google/riscv-dv#620) (taoliug) Signed-off-by: Udi <udij@google.com> |