This removes the manually copied version at dv/uvm/core_ibex/common
and vendors things properly now that the vendor tool supports such
things (this picks up the same OpenTitan version as the previous
commit: lowRISC/opentitan@067272a2).
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
067272a253f4eeed4ae58a9171ee266256528117
* [dv/common] initial support for shadow register (Cindy Chen)
* [rtl/prince] Small fixes for PRINCE cipher logic (Udi Jonnalagadda)
* [dv doc] Fix rendered testplan table (Srikrishna Iyer)
* [prim/dv] Enable coverage collection for PRESENT (Udi Jonnalagadda)
* [dvsim/syn] Minor fix in message reporting (Michael Schaffner)
* [prim] Make prim_clock_inverter a tech specific prim (Michael
Schaffner)
* [vsg] fix _i/_o for several modules (Scott Johnson)
* [doc] Update Licence Headers to fit agreed style (Sam Elliott)
* [vsg] fix _i/_o usage on sram_arbiter (Scott Johnson)
* [vsg] fix _i/_o usage on prim_fifo (Scott Johnson)
* switch to host, primary, or over-arching as appropriate (Scott
Johnson)
* [dvsim/lint/syn] Properly set the errors_seen value to return
nonzero status (Michael Schaffner)
* [dvsim] Fix open() call with Pathlib for older Python versions
(Michael Schaffner)
* [style-lint] Last round of minor fixes to get all targets clean
(Michael Schaffner)
* [prim] Add shadow register primitive (Pirmin Vogel)
* [flash_ctrl] Cosmetic updates enum literals (Srikrishna Iyer)
* [tool/script] delete clean section in make files (Cindy Chen)
* [dvsim] Add git commit and branch info to reports (Michael
Schaffner)
* [dvsim/syn/lint] Add options to selectively sanitize reports
(Michael Schaffner)
* [lint] Update waiver file for prim_generic_pad_wrapper (Michael
Schaffner)
* [prim_pad_wrapper] Update pad wrapper (Michael Schaffner)
* [alert_handler/rtl] priority between ping_ok and sig_int_err (Cindy
Chen)
* [prim] Add a few prim cells needed for clock / resets (Timothy Chen)
* [dv] added default timeout message to DV_SPINWAIT (Srikrishna Iyer)
* [dv] Add mechanism to configure vseq via knobs (Srikrishna Iyer)
* Make the wmask assertion in prim_generic_ram_*p only apply to writes
(Rupert Swarbrick)
* [prim_gate_gen] Recalibrate gate generator for new std cells
(Michael Schaffner)
* [primgen] Use SafeDumper for YAML (Philipp Wagner)
* [primgen] Fix some flake8-reported style issues (Philipp Wagner)
* [prim] Improve extraction of parameter port list (Philipp Wagner)
* [prim] Remove outdated comment from primgen (Philipp Wagner)
* Added missing include prim_assert.sv (Dawid Zimonczyk)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
The idea is that this can supply top_pkg.sv, a top-level thing in
OpenTitan, for DV code we vendor from there. It's probably better to
do this than to directly vendor in OpenTitan's top_pkg, because the
latter has information about e.g. flash memory layout, which doesn't
really have any meaning for Ibex.
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
ebf4663b42a9d81d026db5821b5c8249d54f23a7
* [prim_lfsr] Fix description in core file for FPV (Philipp Wagner)
* [prim_lfsr] Factor out into a separate core file (Philipp Wagner)
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
9ac4f9c8b924b79eb7d3581b29346a612f705751
* Allow verilated top-levels to do work after a simulation completes
(Rupert Swarbrick)
* Add some missing dependencies on lowrisc:prim:assert (Rupert
Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This is manually squashed with a change to import dv_base_reg too, a
new module that was created by Weicai's "csr backdoor support" patch.
It's needed because it is a dependency of dv_lib.
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
c91b50f357a76dae2ada104e397f6a91f72a33da
* [prim_ram*_adv] Update core files and add prim_util dependency
(Michael Schaffner)
* [prim_ram*_adv] Implement Byte parity in prim_ram*_adv (Michael
Schaffner)
* [dvsim] Run tests in "interleaved" order (Rupert Swarbrick)
* [dvsim] Remove unnecessary getattr/setattr calls from SimCfg.py
(Rupert Swarbrick)
* [dv] Add support for multiple ral models (Srikrishna Iyer)
* [rtl] Fix prim flash dependency (Srikrishna Iyer)
* [prim_fifo_sync] Make FIFO output zero when empty (Noah Moroze)
* [dv] csr backdoor support (Weicai Yang)
* [prim] Add a "clog2 width" function (Philipp Wagner)
* [dvsim] Allow max-parallel to be set in the environment (Rupert
Swarbrick)
* [dvsim] Fix --reseed argument (Rupert Swarbrick)
* [prim_ram/rom*_adv] Break out into individual core files (Michael
Schaffner)
* [prim_rom] Align port naming with prim_ram* (Michael Schaffner)
* [dv] Allow a test to have "simple" timestamps (Rupert Swarbrick)
* [dvsim] Improve --help message (Rupert Swarbrick)
* [dvsim] Remove unused --local argument (Rupert Swarbrick)
* [dvsim] Small tidy-ups to mode selection in SimCfg.py (Rupert
Swarbrick)
* [fpv] formal compile fix required by VC Formal (Cindy Chen)
* [dvsim] Fix error detection logic in Deploy.py (Rupert Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
Instead of using copies of primitives from OpenTitan, vendor the files
in directly from OpenTitan, and use them.
Benefits:
- Less potential for diverging code between OpenTitan and Ibex, causing
problems when importing Ibex into OT.
- Use of the abstract primitives instead of the generic ones. The
abstract primitives are replaced during synthesis time with
target-dependent implementations. For simulation, nothing changes. For
synthesis for a given target technology (e.g. a specific ASIC or FPGA
technology), the primitives system can be instructed to choose
optimized versions (if available).
This is most relevant for the icache, which hard-coded the generic
SRAM primitive before. This primitive is always implemented as
registers. By using the abstract primitive (prim_ram_1p) instead, the
RAMs can be replaced with memory-compiler-generated ones if necessary.
There are no real draw-backs, but a couple points to be aware of:
- Our ram_1p and ram_2p implementations are kept as wrapper around the
primitives, since their interface deviates slightly from the one in
prim_ram*. This also includes a rather unfortunate naming confusion
around rvalid, which means "read data valid" in the OpenTitan advanced
RAM primitives (prim_ram_1p_adv for example), but means "ack" in
PULP-derived IP and in our bus implementation.
- The core_ibex UVM DV doesn't use FuseSoC to generate its file list,
but uses a hard-coded list in `ibex_files.f` instead. Since the
dynamic primitives system requires the use of FuseSoC we need to
provide a stop-gap until this file is removed. Issue #893 tracks
progress on that.
- Dynamic primitives depend no a not-yet-merged feature of FuseSoC
(https://github.com/olofk/fusesoc/pull/391). We depend on the same
functionality in OpenTitan and have instructed users to use a patched
branch of FuseSoC for a long time through `python-requirements.txt`,
so no action is needed for users which are either successfully
interacting with the OpenTitan source code, or have followed our
instructions. All other users will see a reasonably descriptive error
message during a FuseSoC run.
- This commit is massive, but there are no good ways to split it into
bisectable, yet small, chunks. I'm sorry. Reviewers can safely ignore
all code in `vendor/lowrisc_ip`, it's an import from OpenTitan.
- The check_tool_requirements tooling isn't easily vendor-able from
OpenTitan at the moment. I've filed
https://github.com/lowRISC/opentitan/issues/2309 to get that sorted.
- The LFSR primitive doesn't have a own core file, forcing us to include
the catch-all `lowrisc:prim:all` core. I've filed
https://github.com/lowRISC/opentitan/issues/2310 to get that sorted.
https://github.com/lowRISC/opentitan/pull/2311 added the Verilator
memutils to OpenTitan as upstream. This commit is the second part of the
story, removing the code from the Ibex repository, and vendoring it back
in from OpenTitan.
This also superseded #844, which has now been included through
OpenTitan.
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
Since we deleted the lock file in the previous commit, this has no
shortlog, but note that the remote SHA matches that in the grandparent
commit (so we haven't missed anything).
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This commit was generated by running
for hj in $(grep -l opentitan vendor/*.vendor.hjson); do
$opentitan/util/vendor.py -U -c $hj
done
and then squashing together all the resulting commits. It will be
followed by a patch that combines these vendor.hjson files (using the
vendor tool's new "mapping" functionality), but we need a patch first
to get everything in sync before squashing together.
Individual commit messages below:
*****
Update common_ifs to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/common_ifs in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv] This fixes a padctrl reset issue in the chip level tb (Michael
Schaffner)
*****
Update csr_utils to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/csr_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv] csr_excl_item printed msg cleanup (Srikrishna Iyer)
* [dv] Fix top-level mem test (Weicai Yang)
* [doc] Fix typo in CSR exclusions (Michael Schaffner)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)
*****
Update dv_lib to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/dv_lib in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv/chip] fix csr_hw_reset X assertion issue (Cindy Chen)
* [dv] Use phase_ready_to_end to handle end of test (Weicai Yang)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)
*****
Update dv_utils to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/dv_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [dv] Add begin...end around if statement in macro (Weicai Yang)
* [dv] Fix timeout due to too many non-blocking TL accesses (Weicai
Yang)
* [spi_device/dv] Add interrupt seq (Weicai Yang)
*****
Update dvsim to lowRISC/opentitan@249b4c31
Update code from subdir util/dvsim in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dvsim] Enable round-trip of env variables into log (Philipp Wagner)
* [dvsim] Support for running pre-built SW tests (Srikrishna Iyer)
* [dvsim] Print what cmd is executed in the log (Srikrishna Iyer)
* [dvsim] Specify encoding of opened files as UTF-8 (Philipp Wagner)
* [dvsim] Simplify factory methods for FlowCfg (Rupert Swarbrick)
* [dvsim] small fix on css style (Cindy Chen)
* [dvsim] support css format for email (Cindy Chen)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)
*****
Update uvmdvgen to lowRISC/opentitan@249b4c31
Update code from subdir util/uvmdvgen in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [uvmdvgen] Minor env gen fix (Srikrishna Iyer)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)
* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [uvmdvgen] Automate checklist gen, fixes (Srikrishna Iyer)
* [doc] Unify dashboard, manual spec table (Srikrishna Iyer)
* [dvsim] Added fusesoc generator for RAL (Srikrishna Iyer)
Update code from subdir hw/dv/sv/dv_lib in upstream repository
https://github.com/lowRISC/opentitan to revision
1d17b1225d324c81da522c69317335a83edd5ddb
* [dv] Add excl for rstmgr, pwrmgr and fix top-level csr test (Weicai
Yang)
* [dv] Allow dv_lib-based sequences to have different RSP/REQ types
(Rupert Swarbrick)
* [dv] Support WO, RO type for mem (Weicai Yang)
* [dv,sw] SW -> DV tb self-checking mechanism - SV (Srikrishna Iyer)
* [dv/top] Fix csr rw test (Cindy Chen)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
Update code from upstream repository https://github.com/google/riscv-
dv to revision 42264b7782a10848935e995063c212893820e561
* fix pmp generation in bare program mode (Udi Jonnalagadda)
* Use literal instead array concatenation (Daniel Mlynek)
* fix access rights (Daniel Mlynek)
* fix in WA fo Aldec Riviera rand cannot be defined in packed struct
(Daniel Mlynek)
* Fix ius compile error (Weicai Yang)
* fix pmp randomization to adhere to max offset (Udi Jonnalagadda)
* Add options to enable bitmanip by group (google/riscv-dv#532)
(weicaiyang)
* [pmp] Relative addressing scheme to configure pmpaddr (google/riscv-
dv#534) (udinator)
* redunant variable ALDEC_PATH removed (danielmlynek)
* riviera 2020.04 beta initial support (danielmlynek)
* Removed system function call from the gen_section() function
arguments list. (google/riscv-dv#531) (Dariusz Stachańczyk)
* Dynamic arrays declared as parameter changed to const variables.
(google/riscv-dv#530) (danielmlynek)
* enhance pmp configuration to make safe region configurable (Udi
Jonnalagadda)
* Fix a typo in riscvOVPsim (google/riscv-dv#529) (weicaiyang)
Signed-off-by: Udi <udij@google.com>
Update code from upstream repository https://github.com/google/riscv-
dv to revision 3f584adef07b7f04edda8a6ba1dfc01a14df5d98
* update ebreak generation for ML test (Udi Jonnalagadda)
Signed-off-by: Udi <udij@google.com>
Update code from upstream repository https://github.com/google/riscv-
dv to revision 4583049cc2b3469ba9dea56b5e2d75809a89d8f3
* Allow running compile command in LSF (google/riscv-dv#506) (taoliug)
* improve documentation of config options (Udi Jonnalagadda)
* Update AMO region and data sections (google/riscv-dv#503) (taoliug)
* Avoid jumping to a sub program of other harts (google/riscv-dv#502)
(taoliug)
* Use .section for data sections by default (google/riscv-dv#501)
(taoliug)
* create PMP accessible region for exception handlers and start/end
sections (Udi Jonnalagadda)
* minor change to signature_addr passed to generator (google/riscv-
dv#497) (udinator)
* Solve before cconstraints modified (google/riscv-dv#476) (Dariusz
Stachańczyk)
* Move instruction sections together for multi-harts (google/riscv-
dv#495) (taoliug)
* add seed capability to CSR test generation (Udi Jonnalagadda)
* fix pmp/shifted_addr compile warning (google/riscv-dv#493)
(udinator)
* User long jump to switch between different harts (google/riscv-
dv#491) (taoliug)
* Fix s_region generation (google/riscv-dv#487) (taoliug)
* update rv32imc/riscv_pmp_test testlist options (google/riscv-dv#486)
(udinator)
* Fix default value of num_of_harts (google/riscv-dv#485) (taoliug)
* Add shared memory region for multi-harts AMO (google/riscv-dv#484)
(taoliug)
* Add a runtime option num_of_harts (google/riscv-dv#483) (taoliug)
* Add multi-thread support (google/riscv-dv#482) (taoliug)
Signed-off-by: Udi <udij@google.com>
Update code from upstream repository https://github.com/google/riscv-
dv to revision 6e2bc2e01fb20799c9eff29a26852eb1917b977a
* fix a missed syntax error in pmp_cfg (Udi Jonnalagadda)
Signed-off-by: Udi <udij@google.com>
Update code from upstream repository https://github.com/google/riscv-
dv to revision a655f34eb5058da442b38ca010b0d008291c11b5
* Support running C test (google/riscv-dv#453) (Hai Hoang Dang)
* run.py: Do not compare csv file when specified -debug switch
(google/riscv-dv#451) (Hai Hoang Dang)
* adjust location of nested interrupt mstatus.mie enable
(google/riscv-dv#444) (udinator)
* Implement storing the commands that would be executed as a script
(google/riscv-dv#450) (Hai Hoang Dang)
* Move document from README to docs, add HTML preview for the new doc
(google/riscv-dv#448) (taoliug)
* Use single HTML format (google/riscv-dv#447) (taoliug)
* Update HTML document (google/riscv-dv#446) (taoliug)
* Add framework for custom extensions (google/riscv-dv#442) (taoliug)
Signed-off-by: Udi <udij@google.com>
Update code from upstream repository https://github.com/google/riscv-
dv to revision 5b1dd4e2eb11d49d3275da80953efc0c50f90447
* Add compliance mode to coverage model (google/riscv-dv#361)
(taoliug)
* Revert " Make assign_operand become a method of class
RiscvInstructionTraceEntry (google/riscv-dv#357)" (google/riscv-
dv#360) (taoliug)
* Fix script issue (google/riscv-dv#358) (taoliug)
* Make assign_operand become a method of class
RiscvInstructionTraceEntry (google/riscv-dv#357) (Hai Hoang Dang)
* Remove unused variable (google/riscv-dv#348) (Hai Hoang Dang)
* Functional coverage improvement (google/riscv-dv#356) (taoliug)
* Fix list access exception thrown when parsing ovpsim illegal
instruction (Udi Jonnalagadda)
* Add compliance mode and RTL mode to the coverage model
(google/riscv-dv#354) (taoliug)
* Fix lr/sc sequence (google/riscv-dv#353) (taoliug)
* Fix minor illegal instruction issue (google/riscv-dv#351) (taoliug)
* Migrate to new instruction class (google/riscv-dv#350) (taoliug)
* misc issue fixes (google/riscv-dv#349) (taoliug)
* Update README to add contact info for the collaboration request
(google/riscv-dv#347) (taoliug)
* Support running specific multiple tests (google/riscv-dv#346) (Hai
Hoang Dang)
* Fix rv64 coverage model issue (google/riscv-dv#344) (taoliug)
* Fix the link for yaml/base_testlist.yaml (google/riscv-dv#343) (Hai
Hoang Dang)
* refactor debug ROM generation (Udi Jonnalagadda)
* Add a runtime option to run with experimental features
(google/riscv-dv#341) (taoliug)
* Fix a few issues with the new instruction class (google/riscv-
dv#340) (taoliug)
* Improve performance of new experimental instruction class
(google/riscv-dv#339) (taoliug)
* Fix CSR randomization bug when generating loops (google/riscv-
dv#337) (udinator)
* Add support coverage flow for qrun, and minor fix for cov.py
(google/riscv-dv#335) (Hai Hoang Dang)
* [ovpsim] Coding style fixes, fix floating point compare mismatch
(google/riscv-dv#334) (taoliug)
* Fix ius flow issue (google/riscv-dv#333) (taoliug)
* Fix a few new instruction class issues (google/riscv-dv#332)
(taoliug)
* Added two includes and starting variables for adding bitmanip
extension (google/riscv-dv#328) (simond-imperas)
* Integrate experimental instruction class (google/riscv-dv#331)
(taoliug)
* Minor fixes to run.py (google/riscv-dv#330) (taoliug)
* Run.py: minor refactor the code for compile, and simulate
(google/riscv-dv#326) (Hai Hoang Dang)
* Add requirements for install dependencies (google/riscv-dv#325) (Hai
Hoang Dang)
* Adding support qrun simulator (google/riscv-dv#324) (Hai Hoang Dang)
* Add new experimental instruction class (google/riscv-dv#323)
(taoliug)
* Added command line control of coverage and added hooks for vector
coverage development (google/riscv-dv#317) (simond-imperas)
* Fix compilation issue (google/riscv-dv#322) (taoliug)
Signed-off-by: Udi <udij@google.com>
