This allows tests to run to completion. Unfortunately, the core agent
currently has a bug in how it handles errors (if a sequence item
terminates with an error and is followed by a 'req' sequence item, the
test hangs).
I'll fix that in a separate patch soon (and revert this commit), but
don't want the memory agent changes to depend on the fix.
As with the core agent, this doesn't yet have any proper monitoring,
and the testbench has no scoreboard, so we're not actually checking
anything.
However, it *does* implement a slave agent which can respond to
instruction fetches from the icache. This runs a test to completion,
try:
make -C dv/uvm/icache/dv run WAVES=1
Note that the timeout in the hjson file was too small, so this bumps
it to a larger value. A later patch will replace the timeout with a
heartbeat monitor, which should be much cleaner.
The exact dance for the UVM reactive slave is complicated. See
dv/uvm/icache/dv/ibex_icache_mem_agent/README.md for the details.
Since this agent doesn't currently do any monitoring (will be
addressed in a later patch), the monitor_cb clocking block doesn't do
very much at the moment.
The driver_cb clocking block *is* used, though. The input lines are just
those needed to drive things correctly (ready is needed to do
ready/valid signalling properly; err is needed to abort instruction
fetches and do a branch after an error).
I've marked the output signals as negedge: this doesn't really make
any difference to simulation results, since the design samples
everything on posedge, but makes it rather easier to read dumped
waves.
There is more than one icache-specific agent that we need for the
icache testbench, so "ibex_icache_agent" isn't a very helpful name.
This commit was pretty much automated, except for a few spacing
cleanups, with commands like:
git grep -l ibex_icache_agent | \
xargs sed -i 's!ibex_icache_agent!ibex_icache_core_agent!g'
(and then rename the directory and files).
This fills in the sequencer, driver etc. to actually drive signals.
You can "run" a test with
make -C dv/uvm/icache/dv run
This won't do anything useful (it will stop with a timeout) because
there is no memory agent yet.
This patch also includes a hacky test timeout. We'll remove this (or
at least make it bigger) when we start actually running data through
the tests, but this is handy for now because it means simulations
finish without having to pkill them.
Fusesoc has an unfortunate bug[1] where a boolean parameter which has
default true can't be disabled. For now, just make all our boolean
parameters back into integers again. In the future, when that's fixed,
maybe we should switch things back.
[1] https://github.com/olofk/fusesoc/issues/392
- A new parameter and a run-time control bit (DataIndTiming and
data_ind_timing) enabling different behaviour for running security critical
code sections.
- In the new mode, all branches act as if taken, with not-taken
branches executing as a branch to the next instruction.
- This should give similar execution time/power characteristics
regardless of the branch condition.
- Note that with the BranchTargetALU, branches stall an extra cycle in
secure mode to avoid factoring the branch-taken decision into the
branch target address mux.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
IUS lacks support for certain language features used in Ibex (such as
use of $clog2 in localparam definitions) so remove it as a simulator
that can be used by dv.
Previous to this change the entire process would die on an issue with
processing a single log. This alters it so this will just add to the
failure count with the error logged and the log processing continued to
its end.
The previous code correctly dumped to "waves.fsdb" if you had Verdi
installed. Unfortunately, it dumped to the same file name if you
didn't, which was rather confusing.
This patch passes a "DUMP_BASE" environment variable, rather than
"DUMP_FILE", which doesn't include the extension. Then it appends the
correct extension at runtime in the TCL, when we tell VCS what sort of
dumping to do.
The code now also checks for all environment variables before reading
them, allowing defaults if they don't exist. The defaults might not be
what you want, but a syntax error at this point causes VCS to sit
waiting for terminal input (with no stdin!), which is kind of annoying.
I've also removed the copy-pasted Verdi documentation. Apart from
anything else, this is probably copyright, so we shouldn't have a copy
in the repo!
- Add parameters and actual instantiation of icache
- Add a custom CSR in the M-mode custom RW range to enable the cache
- Wire up the cache invalidation signal to trigger on fence.i
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The option to limit the verilator simulation's maximum number of cycles was
implemented in terms of the `time_` variable, which counts half cycles. This
patch makes the limit respect the requested number of full cycles.
The patch divides `time_` by 2, instead of multiplying `term_after_cycles_`
by 2, as that better conveys the intended semantics, and slightly increases
the range of the limit. Related computations were modified for consistency.
When we run sim.py, we get commands to run the simulator from the YAML
file named by the --simulator_yaml argument, which defaults to
yaml/rtl_simulation.yaml.
This patch makes the argument explicit in the Makefile and adds a
dependency on that file for commands that read it.
This fixes a bug mentioned in issue #674, where dumped wave files were
ending up in dv/uvm/core_ibex, rather than a test-specific output
directory.
It turns out that this is because of my change in commit 08fc2a4,
which runs the simulator in the top core_ibex directory, rather than
changing directories each time. We have to do this to make the
parallel LSF flow work (which presumably has never actually been run,
otherwise we'd have noticed it was broken).
There are two ways I can think of getting this to work. Probably the
cleanest approach is to generate a script for each test, which looks
something like "cd test_dir; setup_stuff; run_simulator". This would
work (and is how I've seen it done in the past), but doesn't really
fit in with the string interpolation/YAML stuff we've got here.
Instead, this patch goes for a hackier approach, where we prefix the
simulation command with "env SIM_DIR=<out>" and then use the SIM_DIR
environment variable in the TCL scripts to figure out where to put the
wave file. This is kind of icky long-term, but should work for now.
I've also got rid of the code that appends some extra plusargs and a
log argument to the simulation command; now, the relevant variables
get substituted in and the actual command is found in
rtl_simulation.yaml.
For packed structs used as input/output port, Questa reports
"Defaulting port 'irqs_i' kind to 'var' rather than 'wire'
due to default compile option setting of -svinputport=relaxed."
The relevant help message says:
```
verror 13314:
vlog Message # 13314:
An input port that is declared with a type but without the 'var' keyword
should default to 'wire' for strict LRM conformance. The default compile
option of -svinputport=relaxed is not LRM compliant, and only defaults
4-state scalar or 4-state single dimension vector types to 'wire'.
Consider using -svinputport=net for strict conformance. See the vlog -help
text for other behaviors available with the -svinputport option.
```
In our code base we can rely on the LRM-compliant handling of this
construct and opt into that using `-svinputport=net`.
Fixes#670
This adds a dependency on $(TESTLIST) (which is that file) for each
target that depends on $(TEST_OPTS), a set of command line options
that includes --testlist=$(TESTLIST).
In practice, we could actually just add the dependency to the
$(metadata)/instr_gen.gen.stamp target, since all the other affected
targets transitively depend on that, but this seems a little confusing
so I've made the dependency explicit.
