This matches the priority used in Spike.
This also fixes an issue in the DV where the priority of
external/software/timer interrupts wasn't calculated correctly.
Previously the monitor would emit write transactions the cycle the
request is seen and emit read transactions the cycle the response is
seen. This allowed later write transactions to be emitted before earlier
reads (where a new write transaction is started the cycle a read
response returns).
Now both read and write transactions are emitted when their response is
seen.
In addition the error field from the response is copied into the
transaction.
Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.
Ibex testbench extended to generate the expected bits.
All other top-levels modified to add the new signals (which are mostly
ignored).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
mseccfg and mseccfgh have changed their addresses. This updates to the
newly allocated values.
The ePMP specification is now available as a versioned PDF,
documentation is updated to point to that removing the local PDF copy.
This parameter forces a reset of all registers inside the core. This is
required to guarantee a common starting point for lockstep and thus
prevent spurious lockstep failure alerts.
Another minor change in this commit rearranges the writeback stage
multiplexing to gate incoming lsu write data when not valid. This stops
any X values from the data bus propagating to the register file
signalling (and thus to the lockstep comparison) which would cause the
lockstep alert to be X. It has the side effect of possibly reducing
power consumption in the register file.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
We're already redirecting stdout to sim.log in run_rtl.py. Specifying
'-l' as well meant that VCS opened sim.log in a separate FD.
Suprisingly enough, this mostly worked, but not always! Just write
once :-)
This commits adds a yaml based intermediate format for test results.
compare.py serialises a TestRunResult (a named tuple type) into this
format for each test run it checks. collect_results.py reads them all
back in to produce reports.
Three reports are output:
- regr.log - plain text report much like the one previously produced
- regr_junit.xml, regr_junit_merged.xml - JUnit report format, the
_merged version batches together multiple tests to appear to be a
single test case under a test suite. This gives better results with
Azure's JUnit reporting.
This signal used to be a one shot enable out of reset. We need an option
to pause execution for OpenTitan, so fetch_enable is extended to cover
that.
The signal is already driven low by the testbench at the end of test.
This is moved after the performance counter reads to ensure they can
complete.
Fixes#1105
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Fix the reset polarity in the irq driver (clears irq signals to zero
on reset rather than them being x) plus remove an unused signal.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The test loops around waiting for the core to sleep then sending
interrupts to wake it. In some cases, the sequence sends an interrupt
that isn't enabled. It never gets back to try again with a new interrupt
since the test is waiting to see wfi first. This change removes that
requirement since it is redundant anyway (have to see wfi to sleep).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Commit 700f29b changed things so that details of the various tests
that ran ended up in separate files. This is nice (and important for
running things in parallel), but isn't massively helpful if you use
regr.log to understand what happened from a CI run!
This patch adds the logs again, splitting them up so that failing
tests come before passing ones (since you usually just care about the
failures).
This allows run.py to pass ISA options through to Spike. This relates to
the failure in #1369 (test inserts a bitmanip instruction which Spike
interprets as valid but the core treats as invalid depending on config).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The CSR tests don't currently support multiple configurations
(see #1333). Since the OpenTitan configuration is the only one currently
being run, update this file to pass with that for now.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This patch teaches Make which tests we're actually running (via the
list_tests.py script), which means that we can compare the ISS and RTL
results in parallel rather than serially.
There's a bit of duplicated code (both list_tests.py and sim.py
currently contain the code to get a list of tests and then filter by
Ibex configuration), but this should go away with a later patch that
runs the RTL simulations in parallel in a similar way.
Note: This might seem a little silly: trace comparison takes way less
time than the RTL simulation! The point is that it's probably easier
to work "from the bottom" than to start by parallelising the
simulations themselves.
This makes path calculations a bit easier when it comes to loading
stuff up for comparison (allowing us to move more into the Makefile).
Long-term, it might also allow us to change how we track things
entirely, getting rid of the start-seed part of the output directory
structure.
The prim_buf.sv file in Ibex is a manual copy of a file which is
typically auto-generated by FuseSoC/primgen. However, Ibex DV doesn't
yet run FuseSoC, and we provide a pregenerated copy instead. The
auto-generated file and its copy got out of sync. Fix that by adding the
new Width parameter.
These changes match newer versions of Riviera. They work for all
versions >= 2020.04. Ibex itself only compiles successfully with
version 2021.04, so there's no need to maintain command-line
compatibility with older versions.
This adds the configuration instantiated in Opentitan and adds
missing prim support to allow the TB to run that configuration.
Resolves#1362
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The value of `misa` will change depending on whether M or B are enabled.
The presence and read values of other CSRs may also depend upon the Ibex
configuration. A fix is required to allow riscv_csr_test to deal with
different CSR descriptions for different Ibex configurations. For now
just comment out `misa` from the descriptions file to enable
riscv_csr_test to run on a wider range of configurations.
This adds more instruction categories and corrects various issues in the
categorization code. Further cross coverage has been added including
illegal bins to remove bins that cannot occur.
The concept of using SVAs with cross coverage has been dropped. The
systemverilog scheduling model makes the concept unworkable.
When the simulator terminates with an error code that is reported as a
test failure and the regression continues. A new check for a plain
'Error' message is required to catch simulator reported errors that
don't become a UVM_FATAL or UVM_ERROR message (e.g. hitting an illegal
coverage bin). Previously any such simulation error would kill the whole
regression.
Note that the alert output is tied off for now until an option is added
to reset all registers (otherwise there will be X propagation).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.
There are no functional changes in this commit, only wiring.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
No functional change. These parameters are effectively fixed. Moving
them to the pkg eases top-level wiring of RAM signals.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
f29a0f7a7115e03fba734b1c00691c253aceb07e. The list of OpenTitan
changes that are merged in appears at the bottom of the commit.
There are some manual changes needed to adapt the code to work with
these changes.
- The ICache monitors need some extra types to adapt to the (rather
odd) data model that the OpenTitan dv_lib code now uses, where a
monitor needs to know an agent's associated sequence type.
- Verilator simulations now use MemArea slightly differently
OpenTitan changes:
* [dv] Allow monitor items to have different types from sequence items
(Rupert Swarbrick)
* [dvsim] Fix primary_cfg handling (Srikrishna Iyer)
* [dvsim] Deal with non unicode chars in log files (Srikrishna Iyer)
* [dvsim] Added common build fail patterns (Srikrishna Iyer)
* [dvsim] Minot cleanup to the lint flow (Srikrishna Iyer)
* [dvsim] Minor cleanups to to formal flow (Srikrishna Iyer)
* [dvsim] Fixes to UNR and cov analysis flows (Srikrishna Iyer)
* [dvsim] Very minor cleanup of Deploy class (Srikrishna Iyer)
* [dvsim] LsfLauncher report early errors as F (Srikrishna Iyer)
* [dvsim] Minor fix in clean_odirs function (Srikrishna Iyer)
* [chip dv] Set +sw_images as comma-separated list (Srikrishna Iyer)
* [flash_ctrl] Split tl intefaces for flash_ctrl and prim_flash_cfg
(Timothy Chen)
* [keymgr] Fix input value checks (Timothy Chen)
* [formal/script] Update generic formal flow naming from `fpv` to
`formal` (Cindy Chen)
* [top, prim] Address wmask and data width mismatch issue (Timothy
Chen)
* [dvsim] Add GUI mode for running simulations (Srikrishna Iyer)
* [dv] Fix reg backdoor (Weicai Yang)
* [dpi] Make an "ECC32" flavour of MemArea (Rupert Swarbrick)
* [uvmdvgen] Fix has_interrupts in env_cfg (Cindy Chen)
* [dvsim] Keep dependencies list (Srikrishna Iyer)
* [prim_prince] Reverse the k0||k1 mapping to match with the paper
(Michael Schaffner)
* [dvsim] Fix printing of last 10 lines (Srikrishna Iyer)
* [primgen] Minor fix to enable types with underscores (Michael
Schaffner)
* [dvsim] Prevent command echo suppression (Srikrishna Iyer)
* [dvsim] Spot fixes for LSF and internal launcher (Srikrishna Iyer)
* [sva] csr assertion dependency update (Cindy Chen)
* [memutil] Change DpiMemUtil so that it no longer owns MemAreas
(Rupert Swarbrick)
* [memutil] Factor out MemArea as a class (Rupert Swarbrick)
* [prim] Split out PRESENT and PRINCE support from prim:all (Rupert
Swarbrick)
* [fpv/otp_ctrl] Disable assertions due to lc_esc_en (Cindy Chen)
* [prim_prince] Annotate some arrays to avoid UNOPTFLAT warnings
(Rupert Swarbrick)
* [top] Hook up latest ast ports and complete a few other integration
(Timothy Chen)
* Eliminate `#pragma once` in favor of include guards (Chris Frantz)
* [sw,dv] Update headers to pass fix_include_guards.py (Alex Bradbury)
* [xbar/dv] Fix assertion error due to short reset (Weicai Yang)
* [sram] Add memory initialization (Timothy Chen)
* [uvmdvgen] Update links in checklist template (Philipp Wagner)
* [dv/uvmdvgen] Add comment for testplan (Cindy Chen)
* [dv/top_earlgrey] chip csr_aliasing timeout (Cindy Chen)
* [dvsim] Cosmetic updates to launcher methods (Srikrishna Iyer)
* [dv] Update csr_wr to support field write (Weicai Yang)
* [dv/common] Fix regression warnings (Cindy Chen)
* [dv] Get blocks with multiple device interfaces working with chip DV
(Rupert Swarbrick)
* [doc] Use relative links in Hjson-related shortcodes (Philipp
Wagner)
* [dvsim] minor enhancement to clean_odir (Srikrishna Iyer)
* [dvsim] Statically display jobs' status (Srikrishna Iyer)
* [dvsim] Do weighted scheduling of jobs (Srikrishna Iyer)
* [dvsim] Schedule jobs by dependency (Srikrishna Iyer)
* [dv] Xcelium UNR typo (Srikrishna Iyer)
* [dvsim] Implement LsfLauncher (Srikrishna Iyer)
* [dv/chip] solve same_csr_outstanding_timeout (Cindy Chen)
* [dv] make dv_base_agent work for high-level agent (Weicai Yang)
* [tools/dv] added UNR flow for xcelium (Rasmus Madsen)
* [prim] Split prim:subreg out of prim:all (Rupert Swarbrick)
* [prim] Split prim_alert_* out of prim:all (Rupert Swarbrick)
* [prim] Split out fifos into a prim_fifo core (Rupert Swarbrick)
* [prim] Split out arbiters into a prim_arbiter core (Rupert
Swarbrick)
* [prim] Make prim:flop_2sync depend on prim:flop (Rupert Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
