`no_nmi` in irq_raise_seq and irq_raise_single_seq would always cause an
NMI to be raised if it was set. This alters it to have the same
behaviour as `no_fast`. Setting `no_nmi` prevents an NMI from being
produced by the sequences, leaving it clears allows an NMI to be
produced but doesn't force it. This allows tests which can deal with NMI
along with other IRQs to fully randomise IRQs.
A new `irq_raise_nmi_seq` is provided for tests that specifically want
an NMI.
this test is arbitrarily failing in regressions on a Spike timeout,
temporarily remove this to avoid blocking.
@udinator to fix this in the near future.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
This PR adds functionality to filter out tests during regressions for a
particular config.
e.g. if a full regression is kicked off using the `small` config, we
don't want to attempt to run any PMP and bitmanip tests as the RTL
parameter-set will not support it.
To do this, a new YAML field called `rtl_params` is added to relevant
test entries, to indicate what parameters (if any) are required to be
able to run the particular test, along with the required value of said
parameters.
`sim.py` will then parse this field (if it exists), and using
information from `ibex_configs.yaml` pertaining to the current config,
will remove tests from being run on-the-fly.
This also gives us the convenient side effect of not having to re-run
instruction generation if there is a parameter/config mismatch, we can
just rerun the RTL compilation and simulation stages safely.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
Currently, the `cov` step in the DV Makefile will only merge coverage
databases emitted directly from Ibex simulations, and will not pick up
any coverage databases generated by the RISCV-DV functional coverage
flow.
This PR updates the `gen_cov()` function in `sim.py` to recursively
search for any generated coverage directories and then merges them all.
Resultant coverage reports include all code coverage, Ibex functional
coverage, and RISCV-DV functional coverage.
The coverage-related targets in the Makefile have also been renamed to
improve clarity.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
The UVM log should be checked for failures before attempting to process
the core trace log. A simulation failure could mean the trace log
doesn't exist and is is preferable to report the simulation error from
the log rather than trace not found as a failure cause.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0b625258549e733082c12e5dc749f05aefb07d5a
* Add a knob to use rounding mode from the instruction (google/riscv-
dv#767) (taoliug)
* Add rounding mode support for floating point arithmetic instructions
(google/riscv-dv#766) (taoliug)
* Fix syntax issue (google/riscv-dv#765) (taoliug)
* Add riscv_amo_instr (aneels3)
* convert string to enum type (ishita71)
* Remove unintended errors in the coverage flow (google/riscv-dv#757)
(taoliug)
* Fix c_test handling in the YAML testlist (google/riscv-dv#756)
(taoliug)
* Add support for new Spike trace format (google/riscv-dv#755) (Daniel
Bates)
* Fixgoogle/riscv-dv#751 for floating point coverage (Weicai Yang)
* Fix issues with implemented TODO's (aneels3)
* fix randomize_gpr (aneels3)
* Add file riscv_b_instr.py (ishita71)
* add std_randomize todo (pvipsyash)
* Add todo for floating_point test (ShraddhaDevaiya)
* Add scripts to integrate with Metrics regression platform (Aimee
Sutton)
Includes a fix to dv/uvm/core_ibex/sim.py to use `asm_test` rather than
`asm_tests` due to changes in RISCV-DV
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
riscv_interrupt_instr_test and riscv_debug_instr_test aim to produce
interrupt and debug requests once per unique instruction they've seen.
One exception to this is WFI instructions, as these always require an
interrupt or debug request to wake the core. This fixes two timeout
issues with WFI instructions.
1. The return value of `decode_instruction` is used to determine whether
an instruction should have an interrupt or debug request generated
for it. For WFI this must always happen or the test will hang.
2. Before calling check_stimulus in a test the testbench waits for 50
clock cycles. For the riscv_interrupt_instr_test and
riscv_debug_instr_test if a WFI is executed during these 50 cycles
the test will hang. This adds a check to see if the core has gone to
sleep in those tests and if so sends interrupt/debug stimulus to wake
it up.
The `driver_tick` DPI call drove inputs directly but was being scheduled
in an undefined order with other always_ff blocks. This results in a
race condition where some always_ff blocks see old inputs and others see
new in the same clock tick. Instead use values from `driver_tick` to
perform NBA updates and avoid the race condition.
* Handle missing log files with error messages rather than terminating
on unhandled exceptions
* Output potential failure causes from sim log file into regression log
* Alter per test output to make it clearer what line corresponds to what
test
* Only output [PASSED] or [FAILED] a single time per test
* Don't output [PASSED] where sim log is good but ISS comparison is not
In UVM 1.2, at least, uvm_component (a base class of
core_ibex_base_test) still has a method called run(). Ironically, this
has been renamed to "run_phase" to avoid conflicting with user names,
but the old-style phase names still exist at the moment.
Rename our copy of the phase object to cur_run_phase, which doesn't
conflict. Also, set it back to null at the end of the run_phase()
task. We shouldn't ever use it afterwards, and it's probably a good
idea to explode with a null object error if we do.
The previous code contained
wait (dut_vif.dut_cb.priv_mode === select_mode())
and VCS warns that this wait block will only trigger on changes to
explicit arguments. That is, if the in_nested_trap field changes, so
the return value of the select_mode() method would change to match
priv_mode, the wait statement won't finish.
This patch explicitly stores a snapshot of the value of select_mode()
just before the wait line. I think this is the intended behaviour, and
will no longer trigger warnings from VCS.
This silences VCS warnings about the DUT having missing port
connections. It doesn't add any actual testing for these signals.
The patch also re-orders the signals to match the order in
ibex_core_tracing.sv, to make it easier to spot what's going on by
eye.
I wonder whether we could use some form of quoting to allow
"32'h8000_0000" to get through Riviera's TCL, but we don't have any
way to test, so let's go with the easy option.
Forward a currently unused parameter.
Disable error exit for warnings. Newer Verilator versions will fail if
for example parameters are unused. As this test does not cover
everything, allow those warning to be printed, but not fail the build.
These changes correspond to similar changes in the prefetch buffer to
support branch prediction. A registered version of fill_ext_done was
required to prevent a combinational loop from branch_i in to valid_o
out.
Multiplexing priorities for fifo_addr have been swapped to match
fetch_addr_d in the same module and all similar multiplexing in the
icache (prioritize incoming branch_i over branch_mispredict_i). Note
however that it is not expected that these conditions will actually
occur together, and an assertion has been added to check that.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Amusingly, there was also actually a bug in the combo sequence logic:
it took seq_idx to be the number of sequences that we'd run so far,
but it is actually an index that chooses which sequence we're about to
run.
dvsim.py runs make as a subprocess, which gets rather confused if
MAKEFLAGS appears in its environment. The proper fix is to clear them
from the environment in the dvsim command: we'll do that on the
OpenTitan side[1] and can revert this patch once that change is vendored
in.
[1] https://github.com/lowRISC/opentitan/pull/4325
This gets the rest of the support code needed for dvsim (which we
currently duplicate). The patch:
- adds the relevant directories to the vendoring file
- adds a patch to rewrite some OpenTitan-specific bits
- adds a "common_project_cfg.hjson"
- re-runs the vendoring tool
This patch won't yet change how DV code runs; we also need to redirect
a couple of paths and delete dv/uvm/data for that. This will happen in
the next patch.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This commit amends some paths in the vendoring hjson file (and updates
config files to use things at the new paths). Finally it re-runs the
vendoring tool:
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
92e9242424c72c59008e267dd3779e2af5ec8e83
which just ends up with a load of file renames.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This makes changes to support Cadence Xcelium 20.09.001.
Cadence recommends that disabling forks should be done using a "disable fork;" statement, not the "disable fork_process_label;" construct.
The "disable fork_process_label" construct for forks is not defined in the IEEE Std 1800-2017 LRM. See section 9.6.2 of the LRM (2017).
For a more detailed explanation, please see the description from my colleague in Issue #1174: https://github.com/lowRISC/ibex/issues/1174.
In many cases, Xcelium will ignore a disable statement if it is not in the "disable fork;" form.
This causes problems in many tests, most notably in the riscv_reset_test.
Processes not being disabled when reset is asserted cause not just test failures, but the entire regression to crash.
Most changes here are simple substitutes of "disable fork;" where "disable label;" was.
Some changes in core_ibex_test_lib.sv require the layout of the fork to be adjusted.
Signed-off-by: CathalMCrevinn <cathal_minnock@crevinn.com>
This PR slightly modifies how we wait for the end of an Ibex sim.
Currently we wait on dut_vif.dut_cb.ecall, which will be delayed by a
cycle as it is in a clocking block.
However we should end the test immediately when an ecall is seen, so we
should rather wait on dut_vif.ecall instead to be more accurate and
prevent potential race conditions caused by irq/debug stimulus being
sent on the same cycle as an ecall instruction is executed by the core.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
Testbench computation of next PC when single stepping was broken. A
branch may stall before branch_set is asserted and this wasn't being
taken into account. Where the branch target ALU is present branch_set
can be set on the first cycle of the branch so this bug wasn't apparent.
Even with the branch target ALU the branch may stall awaiting the result
of a load when the writeback stage is present.
To make matters more complicated for a jump the PC being jumped to is
only available when jump_set is asserted which happens whilst the jump
instruction is stalling.
This alters the riscv_debug_single_step_test so when waiting for a
single step it looks for either a branch_set or jump_set signal being
asserted. Otherwise it waits until the instruction has unstalled. This
should give correct behaviour in all scenarios (potentially further
thought required where exceptions and interrupts occur).
Fixes#1167
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
This PR makes changes to support Cadence Xcelium 20.09.001
Compile error 1: Fixed the following rtl compile error in ibex_cs_registers.sv
assign tselect_rdata = {'b0, tselect_q};
|
xmvlog: *E,NONOWD (/proj/riscv_ibex/users/paulok/lowRISC/ibex_1/rtl/ibex_cs_registers.sv,1288|30): Illegal use of a constant without an explicit width specification [4.1.14(IEEE)].
Compile error 2: Fixed the following DV compile error in ibex_mem_intf.sv
.data_req_o (data_mem_vif.request ),
|
xmelab: *E,ICDCBA (./tb/core_ibex_tb_top.sv,89|14): Illegal combination of driver and output clockvar to variable 'request' detected (output clockvar found in clocking block at line 25 in file ./common/ibex_mem_intf_agent/ibex_mem_intf.sv).
Simulation probes: Fixed issue with probing in yaml for xrun and added licqueue.
Signed-off-by: Paul OKeeffe <paul_okeeffe@crevinn.com>
For some bizarre reason VCS includes DPI code that has smart
quotes (yes, smart quotes) around some #error macros. Recent GCC
versions (g++ >= 10.2) have got proper support for UTF-8, which is
nice but makes them choke on these input files.
Passing -fno-extended-identifiers tells GCC to go back to the days of
yore and pretend that everything is ASCII, and all is well again!
Obviously the right fix is not to embed smart quotes in C++ code, but
that's not something in our control :-(
We have an order-only dependency on the output directory in the rule
for $(sim-cfg-mk). If that output directory happens to be called
"sim", we now have a dependency on "sim". But that's the name of a
phony rule that runs the simulation, which means we end up doing stuff
in a strange order and defeating the variable dumping in the
dependency tracking, causing a spurious rebuild.
This patch defines a variable called OUT-DIR, which is OUT with a
trailing '/' appended. We use it uniformly in the rest of the file
but (I think) it's probably only actually needed in the dependency for
$(sim-cfg-mk). Now, the rule depends on "sim/", which isn't the name
of a phony rule, and all is well.
This PR makes a few changes to how we convert the Ibex trace logs into
CSV format for the riscv-dv functional coverage flow.
1) We now write an entry for every executed instruction into the output
CSV file, as not doing this will skew functional coverage results.
2) We now parse and organize instruction operands a little differently,
to match recent updates to the CSV format (in the upstream riscv-dv
repo).
Operands for instructions that look like this:
`<instr> <rd>, <rs1>(<imm>)`
are now displayed in the CSV file as `<rd>,<rs1>,<imm>` whereas
previously they were displayed as `<rd>,<imm>,<rs1>`.
3) The parsing script now supports bitmanipulation pseudo-instructions.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
