Commit graph

243 commits

Author SHA1 Message Date
Greg Chadwick
c0f67946f2 [rtl,doc] Add double fault detection.
Fixes #1117
2022-01-25 15:05:39 +00:00
Greg Chadwick
97fa5cf280 [rtl,doc] Add customisable PMP reset values
Fixes #1423
2022-01-24 10:01:36 +00:00
Canberk Topal
187944c417 [icache] Add RAM Primitives for scrambling
This commit includes switching to a scrambling RAM primitive for
ICache data and tag RAMs. Also introduces minor changes to ICache
to handle scrambling key valid signal.

It also includes a minor bug fix regarding not initializing
`fill_way_q` signal without ResetAll parameter. When the parameter
is not set and we have our first hit right after ICache enables,
the signal hangs.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2022-01-19 14:59:43 +00:00
Greg Chadwick
756610800b [doc] Fix config and expand max-width of docs 2022-01-11 12:49:04 +00:00
Greg Chadwick
596b4d7e92 [doc] Add new Ibex testplan 2022-01-11 12:49:04 +00:00
Greg Chadwick
a5c55f132e [dv] Add initial coverage plan 2022-01-06 13:47:04 +00:00
Pirmin Vogel
410ffd349d [bitmanip, doc] Update info on bitmanip support and area numbers
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2021-12-16 14:18:00 +01:00
Pirmin Vogel
16d6f5ea2b [rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0
This invovles the following changes:
- Rename pcnt to cpop
- Switch encoding of max and minu
- Remove rev from Balanced version, only available in Full version via
  grev (Zbp)
- Include sext.b/h (previously in Zb_tmp)
- Remove slo[i] and sro[i] from Balanced version, only available in Full
  version (Zbp)

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2021-12-03 22:43:05 +01:00
Pirmin Vogel
71b43a83e2 [rtl, bitmanip] Rename bext/bdep to bcompress/bdecompress
This change is related to the bitmanip draft version 0.94. It's needed
as in draft version 0.93 as well as in version 1.00 sbext from Zbs
changes to bext, leading to two completely different instructions having
the same name.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2021-12-03 22:43:05 +01:00
Michael Schaffner
169785d071 [secded] Switch to inverted ECC codes
Signed-off-by: Michael Schaffner <msf@google.com>
2021-12-02 15:14:11 -08:00
Greg Chadwick
c3dd66e9fa [cosim] Update documentation for cosim
Also adjusts quick install instructions to use /opt/spike-cosim as
that's the path used by the pre-packaged version.
2021-11-12 09:39:38 +00:00
Tom Roberts
cfeef7e864 [doc] Update DIT documentation for unaligned ld/st
Relates to #1414

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-10-19 14:06:53 +01:00
Greg Chadwick
416ecb10df [dv] Add co-simulation environment support to UVM testbench 2021-10-15 11:30:35 +01:00
Greg Chadwick
f4e3eefcfb [rtl,dv,doc] Flip priority of fast interrupts
This matches the priority used in Spike.

This also fixes an issue in the DV where the priority of
external/software/timer interrupts wasn't calculated correctly.
2021-10-15 11:30:35 +01:00
Greg Chadwick
6815e7b714 [rtl] Implement mvendorid/marchid/mimpid CSRs 2021-08-31 17:39:01 +01:00
Tom Roberts
48f11c6733 [rtl] Add bus integrity checking
Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.

Ibex testbench extended to generate the expected bits.

All other top-levels modified to add the new signals (which are mostly
ignored).

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-08-26 16:55:26 +01:00
Pirmin Vogel
14115ea3a8 [util] Document minimal requirement for Xilinx Vivado
This is related to lowRISC/Ibex#1425.
2021-08-26 14:42:26 +02:00
Tom Roberts
65bf9c94f9 [rtl] Add LFSR permutation option
Random constants are sent through the hierarchy as parameters in-line
with other OpenTitan modules.

Further detail on this mechanism can be found in lowrisc/opentitan#2229

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-08-10 16:13:02 +01:00
Greg Chadwick
dbc2b6f5dc [rtl/doc] Update ePMP CSR addresses and documentation
mseccfg and mseccfgh have changed their addresses. This updates to the
newly allocated values.

The ePMP specification is now available as a versioned PDF,
documentation is updated to point to that removing the local PDF copy.
2021-08-05 08:01:56 +01:00
Tom Roberts
6daae3509a [rtl] Modify fetch_en_i behavior
This signal used to be a one shot enable out of reset. We need an option
to pause execution for OpenTitan, so fetch_enable is extended to cover
that.

The signal is already driven low by the testbench at the end of test.
This is moved after the performance counter reads to ensure they can
complete.

Fixes #1105

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-06-23 09:16:27 +01:00
Rupert Swarbrick
7ceff60749 Describe where to find a RISC-V toolchain 2021-06-08 15:41:02 +01:00
Philipp Wagner
71a8763553 [doc] Fix building with sphinxcontrib-wavedrom 3.x
sphinxcontrib-wavedrom 3.x uses wavedrom-cli by default, which can't be
installed on ReadTheDocs. Use the wavedrompy library again instead.
2021-05-11 18:28:56 +01:00
Philipp Wagner
252dde8225 [doc] Require Sphinx 3 until wavedrom is compatible
Sphinx 4 removed some deprecated functionality that was still used by
sphinxcontrib-wavedrom. Use Sphinx 3 until wavedrom releases an updated
version.
2021-05-11 18:28:56 +01:00
Tom Roberts
7ac218f3ae [rtl] Wire scan_rst_ni through ibex_top_tracing
Better to have the tracing top consistent with the non-tracing top.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-04-21 12:41:24 +01:00
Timothy Chen
33cca5e127 [ibex] Add reset bypass controls
Signed-off-by: Timothy Chen <timothytim@google.com>
2021-04-21 09:14:12 +01:00
Philipp Wagner
48a886a25f Update README to match design
Since this part of the README was written the design moved on. Let's
update it. This update follows the text we have at
https://ibex-core.readthedocs.io/en/latest/index.html.
2021-04-14 11:59:10 +01:00
Tom Roberts
a88f5eb912 [rtl] Add dual core lockstep option
Note that the alert output is tied off for now until an option is added
to reset all registers (otherwise there will be X propagation).

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-04-07 12:07:38 +01:00
Tom Roberts
6a3200929b [rtl] Add a new top level plus wiring
This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.

There are no functional changes in this commit, only wiring.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-04-07 12:07:38 +01:00
Rupert Swarbrick
026db55c89 [util] Document required VCS version
We don't actually run anything that checks this at the moment, but at
least we now have it written down somewhere.
2021-04-06 14:13:22 +01:00
Greg Chadwick
4b43afa533 [doc] Fix table rendering for mseccfg 2021-03-19 10:51:49 +00:00
Greg Chadwick
357b40828f [rtl] Add MSECCFGH CSR
This is the top 32 bits of MSECCFG. It currently has no specified bits
so reads as 0 and ignores writes.
2021-03-19 10:51:49 +00:00
Yusef Karim
62b1a30c7d Fix spacing for bullet points to appear
Bullet points now appear properly for the last paragraph under the Data Independent Timing section.
2021-03-16 07:49:18 +00:00
Tom Roberts
2c75c2b2ec Update lowrisc_ip to lowRISC/opentitan@1ae03937f
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
1ae03937f0bb4b146bb6e736bccb4821bfda556b

* [prim/fifo_async] Add assertions on pointers (Tom Roberts)
* [prim/fifo_async] Add support for Depth <= 2 (Tom Roberts)
* [prim/fifo_async] Code tidy-up (Tom Roberts)
* [top / ast] Continued ast integration (Timothy Chen)
* [dvsim] Use bash when running make underneath (Srikrishna Iyer)
* [prim] Increase maximum width for prim_util_memload to 312 (Greg
  Chadwick)
* [sram_ctrl] Fix potential back-to-back partial write bug (Michael
  Schaffner)
* [dvsim] Fix for lowRISC/opentitan#5527 (Srikrishna Iyer)
* [lint] Waive Verilator UNUSED warnings for packages (Rupert
  Swarbrick)
* [uvmdvgen] Update DV doc path and terminology (Srikrishna Iyer)
* [clkmgr] Fix dft issues (Timothy Chen)
* [util] add `dec` types to prim_secded_pkg (Udi Jonnalagadda)
* [util] minor updates to secded_gen (Udi Jonnalagadda)
* [lint] Fix a bunch of lint warnings related to long lines (>100
  chars) (Michael Schaffner)
* [dv] Update common intr_test seq (Weicai Yang)
* [util] Slight refactor of secded_gen.py (Timothy Chen)
* [tlul] Add memory transmission integrity checks (Timothy Chen)
* [dvsim] Move clean_odirs to `util.py` (Srikrishna Iyer)
* [dvsim] Split Deploy into Deploy and Launcher (Srikrishna Iyer)
* [dvsim] Add utils.TS_FORMAT* vars (Srikrishna Iyer)
* [dv/lock_reg] Update IPs to adopt the lock_reg changes (Cindy Chen)
* [dv/enable_regs] Support enable registers have more than one field
  (Cindy Chen)
* [dv/base_reg] use m_field instead of accessing field (Cindy Chen)
* [dv/sram] add SRAM scrambling model for DV (Udi Jonnalagadda)
* [dv/tools] Updated Coverage flow for xcelium (Rasmus Madsen)

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-03-12 16:15:22 +00:00
Tom Roberts
ee8d1051bb [rtl] Add crash dump outputs
Relates to lowrisc/opentitan#4618

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-03-01 10:12:04 +00:00
Philipp Wagner
65287f7d7b Fix deprecated sphinx html_context usage in conf.py
We were using the old html_context which has been deprecated
for a while. This PR switches to html_css_files instead.
See sphinx-doc/sphinx#8885 for more information.
2021-02-18 12:06:38 +00:00
Greg Chadwick
8defdc4d6c [doc] Add ePMP information 2021-02-01 12:22:49 +00:00
Rupert Swarbrick
b295f07b2d [doc] Update dependency descriptions for Spike/OVPsim
This should match what's going on a bit more accurately. The link to
OVPsim now points at the (free of cost) commercial tool: riscv-ovpsim
doesn't support the bitmanip specification that we're using at the
moment.
2021-01-25 17:41:40 +00:00
Tom Roberts
64ee9a930d [rtl] icache performance updates
Remove the SpeculativeRequest parameter, and replace it with a
policy. If the cache is disabled, make the request on the basis that we
definitely won't hit in the cache and so should make the bus request
asap.

Stop fill buffers from fetching complete cache lines when the cache is
disabled. When the core branches into the middle of a line, the lower
words would normally be fetched to complete the line. This is
unnecessary when the cache is disabled since those words will just be
thrown away and the core will stall while they are being fetched.

These two changes make the performance using the disabled icache the
same as using non-icache prefetch buffer.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2020-12-02 15:10:48 +00:00
Rupert Swarbrick
690f8af65e Update paths for vendored DV code
This commit amends some paths in the vendoring hjson file (and updates
config files to use things at the new paths). Finally it re-runs the
vendoring tool:

  Update code from upstream repository
  https://github.com/lowRISC/opentitan to revision
  92e9242424c72c59008e267dd3779e2af5ec8e83

which just ends up with a load of file renames.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
2020-11-28 12:12:27 +00:00
Greg Chadwick
4a64abdf8f [doc] Update info on simulators for verification
A few tweaks to fix broken links, make explanations more clear and
update the information to reflect the present (e.g. Spike master now
implements bit-manip, the seperate branch is gone).
2020-11-13 11:38:01 +00:00
Tom Roberts
5826af8ad9 [rtl] Instantiate shadow CSRs
Instantiate shadow CSRs and wire up to the alert output.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2020-11-05 10:02:24 +00:00
Udi Jonnalagadda
04e720d6da [dv/ibex] Enable icache in Ibex environment
Signed-off-by: Udi Jonnalagadda <udij@google.com>
2020-10-27 09:40:30 +00:00
Philipp Wagner
931b291749 [doc] Mark icache verification as "done for now"
The icache verification is complete until new bugs are found, let's mark
it as such in the docs.
2020-10-23 11:51:33 +01:00
Tobias Wölfel
4431023516 Add support for additional HW breakpoints
Add parameter `DbgHwBreakNum` to configure the number of HW breakpoints.
The parameters controls the number of trigger registers available if
debug support is enabled with `DbgTriggerEn`.

Closes #1070
2020-10-19 13:20:08 +02:00
Tom Roberts
8953d82ca4 [rtl] Various security feature bugfixes
- Document that SecureIbex cannot be used without a multiplier and add
  an assertion in the rtl. This fixes #1080.
- Move the PC checking hardware onto its own parameter to match all the
  other individual security features.
- Make the PC increment behavior more sensible on fetch errors (and make
  it match the icache behavior). Factor this into the PC increment check
  to prevent false triggering, fixes #1094.
- Stop the PC mismatch checker firing on dummy instructions, fixes
  #1095.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2020-10-14 15:46:10 +01:00
Tobias Wölfel
bcbf1a7adf [rtl] Add plusarg to disable trace log
Option to control the state of the Ibex tracer.
Defaults to enable, but allows a setting to disable the trace log.

In long running simulations this file can get quite big and the contents
might not be needed. Use the argument `+ibex_tracer_enable=0` to prevent
the creation of the file.
2020-10-13 15:23:22 +02:00
Philipp Wagner
830b7f7206 Restructure documentation
Restructure the existing documentation to group the content by intended
audience. This produces four sections:

* An introduction section, relevant to "newcomers" to Ibex.
* An user guide, intended for hardware designers (integrators) and
  software developers who want to integrate Ibex, and develop software
  for it.
* A reference guide, which provides background information on the
  design. This section is essential when working on Ibex, and also
  documents our design decisions.
* A developer guide aimed at people modifying Ibex itself. It consists
  mostly of process and tool documentation: how to run the verification
  after a code change, how to use GitHub, etc.

This commit is large, but text is mostly unchanged. A couple of
introductions and tables of content were added, but no significant
changes to the text have been made. These will be done in follow-ups.

Signed-off-by: Philipp Wagner <phw@lowrisc.org>
2020-09-28 22:30:00 +01:00
Greg Chadwick
2f1b95d214 [doc] Document branch prediction configuration 2020-08-27 11:25:17 +01:00
Pirmin Vogel
9559bbb6ff Add RegFile parameter for selecting register file implementation
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2020-08-21 14:20:34 +02:00
Pirmin Vogel
4c3f1e8a3b Doc support for overriding enum/string parameters at the top level
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2020-08-20 11:50:08 +02:00