The important change is that we now tell the user to configure spike
with --enable-misaligned. This is needed because Ibex handles
misaligned loads and stores rather than jumping to a trap handler (the
default behaviour in spike).
There's also a little more information about where you can find the
various tools and how to set them up.
Note that the existing deep links to riscv-dv's documentation
bit-rotted at the start of February.
Add a section on supported tools to the Ibex documentation. Populate it
with my knowledge about tools we've tried. That's a starting point: we
need to add more version numbers and other information as we collect
more data points.
The Verilator version is taken from the new tool_requirements.py file
and inserted into Sphinx.
* Integrate option to implement a multiplier using 3 parallel 17 bit
multipliers in order to compute MUL instructions in 1 cycle
MULH in 2 cycles.
* Add parameter SingleCycleMultiply to select single cycle
multiplication.
The single cycle multiplication capability is intended for FPGA
targets. Using three parallel multiplication units improves performance
of multiplication operations at the cost of DSP primitives. For ASIC
targets, the area consumed by the multiplication structure will grow
approximately 3-4x.
The functionality is selected within the module using the parameter
`SingleCycleMultiply`. From the top level it can be chosen by setting
the parameter `MultiplierImplementation` to 'single_cc'.
Signed-off-by: ganoam <gnoam@live.com>
- The slow multiplier is modified to terminate iterations early instead
of always going the full 32 iterations for `MUL` instructions.
- Multiplications now terminate early after clog2(`op_b`) iterations.
- The slow multiplier can be further optimized by swapping the smaller
operand into `op_b` when in the `MD_IDLE` state.
This commit adds a register file designed to be synthesized into FPGA
synchronous-write / asynchronous-read design elements.
For the artya7-100 example, the register file is implemented by 12
RAM32M primitives, conserving approximately 600 Logic LUTs and 1000
flip-flops at the expense of 48 LUTRAMs.
Signed-off-by: ganoam <gnoam@live.com>
Refactors performance counters so only flops that are required from the
given parameters are explicitly elaborated without relying on
optimization to remove unused flops.
Fixes#473
- Add the minimum amount of trigger system to support GDB hbreak
- Only a single trigger is implemented
- Only instruction address matching
- Only break into debug mode (no native debug)
- Fixes#382
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
lowRISC provides commercial support for Ibex, mention that in the
licensing page if people are looking for such an offering.
Can be extended in the future as we know of more companies offering
support.
The ibex_tracer module implements an execution tracer, observing the
execution flow and writing a human-readable execution trace. The trace
information is coming from the RVFI signals, as specified at
https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md.
The existing implementation was tailored for use in ModelSim and other
commercial simulators, and used SystemVerilog features which are not
supported in Verilator or Icarus Verilog, such as classes, queues and
non-standard format specifiers (e.g. the `-` specifier for right-aligned
output). Being unable to see an execution trace when using Verilator
significantly reduced productivity and its usefulness.
This commit refactors the tracer to only use SystemVerilog constructs
which are supported in Verilator. While doing so, multiple improvements
were made for correctness and style.
Major changes:
- Improve compatibility with Verilator. Remove many non-synthesizable
SystemVerilog constructs, such as classes and queues.
Use casez instead of casex for better Verilator support (Verilator
doesn't support X).
- Make the decoded output of the tracer match objdump from binutils
exactly. Doing so is beneficial for two reasons: we can easily
cross-check the decoded output from the tracer against the disassembly
produced by objdump (and we did that), and users don't need to get
used to another slighly different disassembly format.
- A plusarg "+ibex_tracer_file_base=ibex_my_trace" can be used to set a
different basename for the trace log file.
Smaller cleanups:
- Remove decoding of reg-reg loads, which were leftover from a PULP
extension.
- Make better use of the data available on the RVFI. Pass all of RVFI
to the tracer, and use the provided data instead of manually
recreating it, e.g. to get register data or the jump target.
- Rename all "instr" abbreviations to "insn". "insn" is what RVFI uses
(and we cannot change that), so for consistency we now always use this
abbreviation across the file.
All CSR names have been imported from binutils' riscv-opc.h file, available at
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=include/opcode/riscv-opc.h
using this small C program:
#include <stdio.h>
#define STR(s) #s
int main(int argc, char **argv) {
printf("unique case (csr_addr)\n");
#define DECLARE_CSR(name, csraddr) \
printf(" 12'd%d: return \"%s\";\n", csraddr, STR(name));
#include "riscv-opc.h"
printf(" default: return $sformatf(\"0x%%x\", csr_addr);\n");
printf("endcase\n");
return 0;
}
The RISC-V compliance test suite for the RV32 I, M, and C extensions has
been executed and traced. The disassembly of all traces have been
compared against traces produced by objdump to ensure identical output.
This PR is based on work by Rahul Behl <raulbehl@gmail.com> in #280.
Thank you Rahul for providing a great starting point for this work!
- Relates to issue #265
- External signals data_rvalid_i and data_err_i were factored
into the external data_req_o signal
- To improve timing, these signals are decoupled
- The second part of an unaligned transaction will now be issued
even if the first received an error response
- The state machine will service the abandoned requests
- pmp_err_q fixed to only update at specific times
- Instantiate generic PMP module
- Wire up I-side and D-side PMP faults
- The output of the PMP check is used to gate external bus requests from the
I-side and LSU
- Each of those units progresses with their request as-if it was granted
externally and registers the PMP error
- The error is then sent to the controller at the appropriate time to trigger
an exception
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
This commit makes the BASE field of the `mtvec` CSR writable to
allow changing the trap-vector base address at runtime without
changing the boot address input. Similar to the boot address,
the trap-vector base address must always be aligned to 256 bytes.
At bootup, the trap-vector base address is initialized to the boot
address.
This commit resolveslowrisc/ibex#118.
Most of this work has been done by @ivanmgribeiro as part of
lowrisc/ibex#193.
This change is slighly painful, but a necessary cleanup around the
tracer.
- We now provide a separate core file for the tracer, called
"ibex_tracer.core" (in line with "ibex_tracer.sv"). The core is called
"lowrisc:ibex:ibex_tracer".
- The toplevel wrapper with tracing enabled got renamed to
"ibex_core_tracing.sv", and the core file is correspondingly called
"ibex_core_tracing.core. The core in it is called
"lowrisc:ibex:ibex_core_tracing".
- Finally to keep symmetry, the toplevel of Ibex itself got renamed in
the core file from "lowrisc:ibex:ibex" to "lowrisc:ibex:ibex_core".
This ensures that we have the same name for the core file, the source
entry point, and the core name.
IMPORTANT NOTE:
If you apply this change and use fusesoc, you need to adjust the name of
the core dependency from "lowrisc:ibex:ibex" to
"lowrisc:ibex:ibex_core".
