For exceptions, the Ibex always jumps to the trap vector base address
specified in `mtvec`. The exception cause is specified in `mcause` with
possibly additional information in `mtval`.
Interrupts are handled in vectored mode as before.
`mtval` can provide additional information to trap handlers.
In case of load/store errors, it holds the failing address.
For illegal instruction exceptions, it holds the illegal instruction.
Performance counters are an optional feature. Disable them by default to
avoid users having them enabled unknowingly and paying the (rather
large) area price for it.
The core handles unaligned instruction fetches by doing two separate
word-aligned instruction fetches. Without this commit, the core can
still output addresses which are not word aligned and relies on the
memory to ignore the LSBs of the address. This is not safe.
The core handles unaligned accesses by doing two separate word-aligned
accesses. Without this commit, the core can still output addresses
which are not word aligned and relies on the memory to ignore the LSBs
of the address. This is not safe.
The core ignores the lowest byte of the boot address and thus does not
support booting from addresses not aligned to 256 bytes. This commit
updates both the documentation accordingly and adds an assert to the
IF stage.
This change has been informed by advice from the lowRISC legal
committee.
The Solderpad 0.51 license states "the Licensor permits any Work
licensed under this License, at the option of the Licensee, to be
treated as licensed under the Apache License Version 2.0". We use this
freedom to convert license markings to Apache 2.0. This commit ensures
that we retain all authorship and copyright attribution information.
Convert the documentation to restructured text. It looks slightly
different to the previous Word document, but can better be handled by
source control. It also automatically handles the versioning.
To build it:
python -m venv venv
source venv/bin/activate
pip install -r requirements.txt
make html
make latexpdf