Commit graph

243 commits

Author SHA1 Message Date
Tobias Wölfel
014c753dde Tracer rewrite
Instantiate tracer module in a separate core file and use only RVFI
signals.
2019-07-11 13:25:18 +01:00
Alex Bradbury
36079d784b Reference the performance counter docs from the CSR doc page 2019-07-10 15:00:55 +01:00
Alex Bradbury
81db2eb1a4 Fix doc typo introduced in #128 2019-07-10 15:00:55 +01:00
Alex Bradbury
33b7904a12 Document mtvec as WARL rather than read-only
mtvec is hard-wired, but isn't read-only as writes don't cause an
exception.
2019-07-10 09:41:08 +01:00
Alex Bradbury
ce042bd350 Document that misa is hard-wired
Fixes #123.
2019-07-10 09:41:08 +01:00
Pirmin Vogel
ca7bbddd4e Doc: remove draft when mentioning RISC-V Priv Spec v.1.11
This version of the spec has been ratified in the meantime.
2019-06-28 18:55:26 +01:00
Pirmin Vogel
2c0aabb6bb Doc: use `csr_num`.FIELD_NAME syntax when discussing CSR fields 2019-06-28 18:55:26 +01:00
Pirmin Vogel
9749120f05 Add mscratch CSR 2019-06-28 18:55:26 +01:00
Pirmin Vogel
07214f626d Switch to RISC-V spec compliant trap handling
For exceptions, the Ibex always jumps to the trap vector base address
specified in `mtvec`. The exception cause is specified in `mcause` with
possibly additional information in `mtval`.

Interrupts are handled in vectored mode as before.
2019-06-28 18:55:26 +01:00
Pirmin Vogel
e9bdbaddd6 Make mtvec CSR compliant to spec
The LSBs indicate the vector mode. They are set to vectored for Ibex.
2019-06-28 18:55:26 +01:00
Pirmin Vogel
b22a6a10de Add mtval CSR
`mtval` can provide additional information to trap handlers.
In case of load/store errors, it holds the failing address.
For illegal instruction exceptions, it holds the illegal instruction.
2019-06-28 18:55:26 +01:00
Pirmin Vogel
4f928b3ad0 Doc: Fix typos 2019-06-26 14:09:23 +01:00
Pirmin Vogel
89b0d3a200 Clarify application scenarios of register file versions 2019-06-26 14:09:23 +01:00
Philipp Wagner
d811c04cce Disable performance counters by default
Performance counters are an optional feature. Disable them by default to
avoid users having them enabled unknowingly and paying the (rather
large) area price for it.
2019-06-25 17:46:07 +01:00
Pirmin Vogel
b7919a7bd3 Make sure instr address output is word aligned
The core handles unaligned instruction fetches by doing two separate
word-aligned instruction fetches. Without this commit, the core can
still output addresses which are not word aligned and relies on the
memory to ignore the LSBs of the address. This is not safe.
2019-06-24 21:37:53 +02:00
Pirmin Vogel
182e10048b Make sure data address output is word aligned
The core handles unaligned accesses by doing two separate word-aligned
accesses. Without this commit, the core can still output addresses
which are not word aligned and relies on the memory to ignore the LSBs
of the address. This is not safe.
2019-06-24 21:37:53 +02:00
Pirmin Vogel
ec3b246f16 Doc: Add debug_req_i to blockdiagram 2019-06-21 14:42:41 +01:00
Pirmin Vogel
d2fd88dc67 Doc: Add new top-level block diagram 2019-06-07 13:49:12 +01:00
Pirmin Vogel
d7810941e3 Doc: Adapt RVFI section, add connection in intro 2019-06-07 13:49:12 +01:00
Pirmin Vogel
b32078138c Doc: Adjust upper left corner: background color, logo etc. 2019-06-07 13:49:12 +01:00
Pirmin Vogel
5c4e6cb4e3 Doc: Update and cleanup 2019-06-07 13:49:12 +01:00
Tobias Wölfel
4bbe38fa52 Update documentation external link 2019-06-06 13:11:26 +01:00
Tobias Wölfel
90796e3800 Add RVFI documentation 2019-06-06 11:21:06 +01:00
Philipp Wagner
6d81447d67 Doc: Switch back to upstream Sphinx
Upstream has now released a new version which includes Stefan's patch to
correctly build the PDFs.

Fixes #41
2019-06-05 12:56:58 +01:00
Pirmin Vogel
effa61c684 Update documentation on CSRs and performance counters 2019-06-03 15:49:21 +01:00
Pirmin Vogel
cb320352b9 Correct bit numbers in PCMR documentation.
These numbers were inverted in the documentation. This commit resolves #15.
2019-06-03 15:49:21 +01:00
Pirmin Vogel
4809737b43 Correct order of exceptions in documentation 2019-05-22 17:02:18 +01:00
Pirmin Vogel
a44e312e74 Update doc to add data_err_i and LSU exceptions 2019-05-21 15:22:21 +01:00
Stefan Wallentowitz
62185d054e Temporarily switch to custom sphinx
Using figures in admonitions did not work so far. A patch was created
and merge is pending. As long as it is not merged, use custom sphinx.

Fixes #24
2019-05-16 13:27:32 +01:00
Stefan Wallentowitz
5d419cbf16 Fix wavedrom versions
Ensure to pickup the correct versions for wavedrom.
2019-05-15 10:34:41 +01:00
Pirmin Vogel
93b0b77f27 Make sure boot_addr_i is aligned to 256 bytes
The core ignores the lowest byte of the boot address and thus does not
support booting from addresses not aligned to 256 bytes. This commit
updates both the documentation accordingly and adds an assert to the
IF stage.
2019-05-10 11:11:19 +01:00
Philipp Wagner
b0cb03ac42 Add a bit of history to the documentation 2019-04-26 15:09:00 +01:00
Philipp Wagner
fb05a65b69 Adjust documentation for new debug support 2019-04-26 15:09:00 +01:00
Philipp Wagner
1b82b1bb7c Adjust documentation for ibex
With the rename from zero-riscy to ibex, and subsequent cleanups, the
documentation needs an update too.
2019-04-26 15:09:00 +01:00
Alex Bradbury
27e68bd76e Convert from Solderpad to standard Apache 2.0 license
This change has been informed by advice from the lowRISC legal
committee.

The Solderpad 0.51 license states "the Licensor permits any Work
licensed under this License, at the option of the Licensee, to be
treated as licensed under the Apache License Version 2.0". We use this
freedom to convert license markings to Apache 2.0. This commit ensures
that we retain all authorship and copyright attribution information.
2019-04-26 15:05:17 +01:00
Stefan Wallentowitz
dc27666c92
Doc: Bump sphinx version 2018-11-23 20:34:47 +01:00
Stefan Wallentowitz
ac9bc39ca3 Doc: Add integration guidance 2018-11-23 17:17:40 +01:00
Stefan Wallentowitz
0dfe79e94e Doc: Add interrupts description 2018-11-23 17:17:38 +01:00
Stefan Wallentowitz
52ffb372a3 Doc: note difference to LSU wrt to address stability 2018-11-23 17:17:34 +01:00
Stefan Wallentowitz
99964c84d2 Doc: Inline documentation of waveforms
So far I used wavedrom for rendering, but that required external
tooling. After patching the extension, sphinx can now render inline
waveforms!
2018-11-21 16:09:02 +01:00
Stefan Wallentowitz
f376a1e6ab Replace images with wavedrom images 2018-11-13 17:05:49 +01:00
Stefan Wallentowitz
c6eeb34f57 Convert documentation to restructured text
Convert the documentation to restructured text. It looks slightly
different to the previous Word document, but can better be handled by
source control. It also automatically handles the versioning.

To build it:

    python -m venv venv
    source venv/bin/activate
    pip install -r requirements.txt
    make html
    make latexpdf
2018-11-13 16:21:47 +01:00
Pasquale Davide Schiavone
8b685e78a2 added document to repository 2018-09-28 10:44:58 +02:00