Update code from upstream repository https://github.com/google/riscv-
dv to revision 68e3bcac7293ac79067f0d8196bb973bd7c889cf
* [pmp] Remove restriction on using NAPOT when granularity = 0 (Marno
van der Maas)
* [pmp] Add PMP entries for data in case of MML or MMWP (Marno van der
Maas)
* [pmp] Add already_configured flag to skip address in PMP routine
(Marno van der Maas)
* [pmp] Fix constraint and CSR write test in MML mode (Marno van der
Maas)
* [pmp] Use random address instead of offset for full random test
(Marno van der Maas)
* [pmp] Allow specifying address zero in `+pmp_region_%0d` (Marno van
der Maas)
* [pmp] Randomizing entry for instructions for PMP randomization
(Marno van der Maas)
* [lint] Remove trailing whitespace (Marno van der Maas)
* Tweak CSR constraints for more even read/write distribution (Greg
Chadwick)
* [lint] Replace tabs with spaces (Marno van der Maas)
* [pmp] No PMP exception handler when no PMP support (Greg Chadwick)
* Expand CSR instruction constraint functionality (Greg Chadwick)
* Refactor CSR instruction into their own class (Greg Chadwick)
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
We are running with cosim by default now, and no longer support COSIM=0. Hence
this option and all downstream conditional paths are no longer required.
As well as completely removing the existing non-cosim flow, this commit
significantly refactors the build system to be less reliant on the makefile.
While we still use the Makefile, it is relegated to only providing scheduling
and dependency calculations between the different build steps.
This is possible by moving all of the build metadata into a file on-disk, which
is populated at the start of a new regression, then read and written to by the
different scripts executing the build. Each build step only needs to be passed
the location of this metadata at the top-level, and it can then import all
the information it requires to calculate and perform the next build stage.
This allows better observability into the build, as it is trivial to add new
data to this file, which is also provided as a human-readable yaml version.
It should also allow easier integration into different build systems, as the
dependency on Make is much weaker.
The file metadata.py and test_run_result.py contain the definitions for
these metadata objects. metadata.py defines an object for the whole
regression, while test_run_result.py defines objects for each individual test
performed.
The file riscvdv_interface.py has been created to better isolate the interface
with that project.
The file setup_imports.py has been created to centralize the importing of
python modules from other projects (riscvdv/ot_lowrisc_ip etc.).
Existing python code has been tidied to better conform to PEP8 standard
formatting, and to be more python in general such as using pathlib.Path.
We're seeing many timeouts in this test. This is causing issues for the
nightly regression. Keep the test in so we're aware of any major issues
with it but with far fewer timeouts to help keep the regression healthy.
We'll revisit the required iterations once we've sorted out the issues
with the test.
This refactors the invalidation control logic into an explicit state
machine. The top-level icache_invalid_o signal is also removed.
Replaced with an explicit scramble key request instead.
This has all been done to better deal with corner cases around a new
invalidation being requested whilst another is still going on.
Previously there was a bug wher an invalidation request in the final
cycle of an ongoing invalidation didn't restart the invalidation but did
rotate the scrambling key producing an ECC failure and an alert.
This test is generated differently to all the others, as it exclusively uses a
python script.
The easiest way to make this work with the new test_done signature address is to
detect it as a special case and pass it the new address. The handshaking is only
used for ending the test, so the original address does not matter.
Use the address (signature_addr - 0x4) for a TEST_PASS handshake.
Create new mem_seq_item subscriber port for test_done functionality.
By creating a new, distinct port and subscribing to all incoming memory items,
the existing wait_for_mem_txn() can be used with minor modifications to be
able to choose the port to wait on as an argument to the task.
Because the wait_for_mem_txn() implementation currently uses get() to pop the
latest item from the item_collected queue, having two different forked processes
that both await on this queue is not possible. The simplest solution is to
create a new, seperate port which also subscribes to the sequence_items
broadcast by the mem_if monitor.
Signed-off-by: Harry Callahan <hcallahan@lowrisc.org>
The following changes are made:
- For unimplemented counters corresponding bits in MCOUNTINHIBIT read as
0 not 1
- For MHPMEVENTx we start at x = 3 with the first bit set (0-2
MHPMEVENTx CSRs do not exist)
- When writing an invalid privilege mode to MSTATUS.MPP/DCSR.PRV default
to U rather than M mode.
These new behaviours remain spec compliant and match spike.
Initially the 'B' bit was going to be used to indicate the presence of
the bit-manipulation extension. Now that has been seperated into
multiple smaller extensions the 'B' MISA bit isn't being used and
remains a reserved bit that should read as 0.
For the RV32B configurations where we implement non ratified
bit-manipulation extensions we must set the 'X' bit.
These changes matche the behaviour of spike.
This extends our memory range to be between 0 and
0xFFFF_FFFF. This is needed because in the case of
no match between UVM memory model and spike memory
model, we see a mismatch.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
After vendoring the new changes to the prim IP:
- Reorder `ibex_dv.f` to reflect the dependency on `prim_assert.sv`
- Disable assertion for register file prim onehot check.
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
As Greg pointed out:
When we have an instruction in ID/EX that writes a PMP register that
update gets written to the CSR the same cycle the next instruction
moves from IF to ID/EX with it's PMP check done with the old value.
The solution is to flush the pipeline when we get a PMP CSR write.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
The relevant page [Debug Spec v1.0.0-STABLE, p.53] gives the following
priorities for resolving multiple concurrent reasons for entering debug mode....
DCSR.cause : Explains why Debug Mode was entered.
When there are multiple reasons to enter Debug Mode in a single cycle,
hardware should set cause to the cause with the highest priority.
1: An ebreak instruction was executed. (priority 3)
2: A Trigger Module trigger fired with action=1. (priority 4)
3: The debugger requested entry to Debug Mode using haltreq. (priority 1)
4: The hart single stepped because step was set. (priority 0, lowest)
5: The hart halted directly out of reset due to resethaltreq. (priority 2)
It is also acceptable to report 3 when this happens.
6: The hart halted because it’s part of a halt group. (priority 5, highest)
Harts may report 3 for this cause instead.
Other values are reserved for future use.
Added a patch for riscv_core_setting.sv, which is applied for the small
and experimental-branch-predictor configs.
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
fixup
- Enable epmp in riscv_core_settings.sv
- Bump CI and Spike version in `ci/vars.yml`
- Enable full random PMP test
- Create tests for machine mode lockdown (MML)
- Code execute only, rest read/write
- All regions execute only
- All regions read only
- Create test for machine mode whitelist policy (MMWP)
- Create test for rule lock bypass (RLB)
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
Update code from upstream repository https://github.com/google/riscv-
dv to revision 808fb162d66de5dd0dd2b45fd0b8d1fb1bf170f6
* [scripts] Improve WARL support in gen_csr_test (Greg Chadwick)
* [scripts] Refactor gen_csr_test (Greg Chadwick)
* Allow for WFI in User Mode (Canberk Topal)
* [Smepmp] Fixes `gen_pmp_instr` when MML and MMWP are enabled (Marno
van der Maas)
* Fix typo in mseccfg_reg_t class (aneels3)
* Fixgoogle/riscv-dv#819 (aneels3)
* lib.py, launch process in new session to fix timeout issue (Yannick
Casamatta)
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
This commit sets two different riscv-dv knob to make sure we hit
some holes in our coverpoints.
Activating `enable_timer_irq` for everytime we enable other
interrupts makes sure that we respond to it just like we respond
to other interrupts.
Setting tw=0 makes it so that we would allow WFI in user mode. We
were already randomizing it but for some certain tests, we actually
want to be in a sleep state, which wouldn't happen if tw=0 in user
mode.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This allows us to actually use Icache in our tests beecause
before this commit key_valid was tied to 0 which means everytime
we receive a FENCE.I instruction, we wouldn't be able to successfully
flag inval_done. Which means we weren't probably using ICache correctly.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
In ePMP spec, it specifies as:
```
Executing code with Machine mode privileges is only possible from memory
regions with a matching Mmode-only rule or a locked Shared-Region rule
with executable privileges. Executing code from a region without a
matching rule or with a matching S/U-mode-only rule is denied.
```
This change provides that.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit makes sure that different IRQs are collected in a single
`fcov_irqs` bus correctly. Also changes nmi_taken coverpoint to catch
interrupt taken case for NMI types from the same bus.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Some aspects of the memory response are only relevant to reads. This
introduces outstanding request tracking so we know which outstanding
requests are reads and applies X checks appropriately.
Fixes#1645
This commit fixes how we catch an instruction at WB stage. Before this fix
we were effectively checking opcode of decoded instruction instead.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
The riscv_csr_test does not use cosim but was failing due to lack of a
cosim log. This option skips the stage of pass/fail determination that
looks for that log.
This adds a couple of missing fields to cpuctrl and comments out mcause.
mcause will be added back once RISC-V DV has been updated to support
WARL fields properly.
