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Author SHA1 Message Date
Markus Wegmann
64d80a79e1 Remove special math and bit operations 2016-10-20 22:06:52 +02:00
Markus Wegmann
5445d0a08e Add simplified ALU 2016-10-20 17:17:59 +02:00
Markus Wegmann
99b1849f54 Fix last 2016-10-18 15:34:57 +02:00
Markus Wegmann
89cb4a7b7e Fix last commit 2016-10-18 15:30:35 +02:00
Markus Wegmann
8dad2dce56 Fix wrong assertion due to removing hardware loop support 2016-10-18 15:27:34 +02:00
Markus Wegmann
5caf622c3c Fix wrong syntax in prefetch buffer due to removal of hardware loop 2016-10-18 15:24:05 +02:00
Markus Wegmann
2d0152afe9 Fix missing parameter due to removing of hardware loop 2016-10-18 15:17:08 +02:00
Markus Wegmann
942d5944f7 Remove Hardware Loop 2016-10-18 15:04:28 +02:00
Markus Wegmann
f5fc141ce4 Add switch for Vector support. Remove divider when multiplier removed. 2016-10-17 18:09:04 +02:00
Markus Wegmann
acb09458f7 Add missing MUL_SUPPORT region 2016-10-17 11:57:21 +02:00
Markus Wegmann
2d5f2365c1 Fix MUL_SUPPORT section in controller 2016-10-17 11:54:29 +02:00
Markus Wegmann
783eeb6172 Add missing MUL_SUPPORT directives 2016-10-17 11:51:41 +02:00
Markus Wegmann
bd0728a8d9 Add missing whitespace in ALU module (coding convention) 2016-10-17 11:04:30 +02:00
Markus Wegmann
fbc5c074bc Add RI32M support switch and apply it to all signals 2016-10-17 11:04:00 +02:00
Markus Wegmann
6b42805ee7 Add missing whitespace in section title of multiplier module 2016-10-17 11:02:19 +02:00
Markus Wegmann
16a5f9fb11 Revert "Remove most custom ISA instructions from decoder." 
This reverts commit 5f4989d9cb.

Revert uncommenting the decoder commands to begin with the ALU
 2016-10-17 09:35:43 +02:00
Markus Wegmann
5f4989d9cb Remove most custom ISA instructions from decoder. 2016-10-04 15:03:29 +02:00
Pasquale Davide Schiavone
557f18151c Merge branch 'fix-typos' into 'master' 
Fix some typos

/cc @pasquale.schiavone 

See merge request !8
 2016-09-05 09:52:38 +02:00
Robert Schilling
63666b3105 Fix some typos 2016-09-02 09:22:33 +02:00
Pasquale Davide Schiavone
5338cc01a4 Optimized Clip in ALU and removed trilling white spaces in prefetch_L0_buffer 2016-07-29 10:46:40 +02:00
Pasquale Davide Schiavone
3e1a7b8f45 Optimized shifter in ALU 2016-07-29 09:38:57 +02:00
IGOR LOI
dc7c02a164 updated prefetch buffer, removed bubbles for misaligned 32b instructions during crossword 2016-07-19 18:01:18 +02:00
Pasquale Davide Schiavone
92ae281aab Implemented beqimm and bneimm 2016-07-06 11:39:28 +02:00
Pasquale Davide Schiavone
01f21f7134 Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/riscv 2016-06-27 14:13:21 +02:00
Pasquale Davide Schiavone
d805b5ad42 fix shuffle.sci.h 2016-06-27 14:13:06 +02:00
Francesco Conti
15a7ef0089 Revert "fixes for new ipstools" 
This reverts commit d14327c1b8.
 2016-06-24 10:34:36 +02:00
Francesco Conti
f51c1ebc97 Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/riscv 2016-06-24 00:24:26 +02:00
Gautschi
55d66013ae fixed issue with include file 2016-06-23 14:36:30 +02:00
Gautschi
7f6bb8ebb4 reenabled traces in riscv core 2016-06-23 13:05:25 +02:00
Pasquale Davide Schiavone
4bf318ac63 GCC Shuffle2 Alignment 2016-06-20 09:42:55 +02:00
Pasquale Davide Schiavone
11aa315721 Merge branch 'jalr-invalid-instruction' into 'master' 
Trigger an invalid instruction if jalr op code bits 14:12 are not zero

According to the RISC-V ISA specification 2.1 the bits 15:12 of the `jalr` instruction should be zero. The decoder stage of checks that and aborts the jump if so. However, this is an invalid instruction, which should be signaled.

/cc @pasquale.schiavone 

See merge request !1
 2016-06-15 09:33:44 +02:00
Michael Gautschi
840f500e79 Merge branch 'sv-packages' into 'master' 
Sv packages

moved to sv-packages in the riscv core. (no more defines)

See merge request !3
 2016-06-13 16:27:13 +02:00
Gautschi
5a0ef29719 beautify banners 2016-06-13 16:25:46 +02:00
Michael Gautschi
7f8389cb40 Merge branch 'master' into 'sv-packages' 
Fixed misalignment memory access



See merge request !2
 2016-06-13 16:17:00 +02:00
Robert Schilling
99da96f66b Trigger an invalid instruction if jalr op code bits 14:12 are not zero 2016-06-13 14:37:19 +02:00
Francesco Conti
d14327c1b8 fixes for new ipstools 2016-06-09 19:37:09 +02:00
Pasquale Davide Schiavone
3277a983c7 Fixed misalignment memory access 2016-06-07 14:19:56 +02:00
Gautschi
8a52246a00 moved to package based riscv core 2016-06-03 14:04:44 +02:00
Gautschi
9031aa2398 Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/riscv 2016-06-01 11:33:25 +02:00
Gautschi
59708f4422 fixed NCSIM simulation issue related to riscv_tracer 2016-06-01 11:33:03 +02:00
Pasquale Davide Schiavone
4b70a0ffa0 Fixed vectorial comparison 2016-05-30 12:12:07 +02:00
Pasquale Davide Schiavone
25a7705051 Fixed clip and clipu 2016-05-25 17:20:59 +02:00
Pasquale Davide Schiavone
ccdf02ecf8 Fixed pv.insert 2016-05-19 15:20:52 +02:00
Andreas Traber
5bf76abb66 Fix new behaviour for clb 2016-05-17 11:21:00 +02:00
Andreas Traber
eab2d13bd2 Align ff1 and fl1 with the compiler builtins 2016-05-13 18:22:59 +02:00
Andreas Traber
70968a1232 add pv.shuffleI1, pv.shuffleI2, pv.shuffleI3 instructions 2016-05-13 16:20:32 +02:00
Andreas Traber
b2591ce917 add an external resume signal for debug 2016-05-12 12:24:29 +02:00
Andreas Traber
b10a591c75 During first fetch, save PC from IF instead of ID 2016-05-11 12:58:52 +02:00
Andreas Traber
4630c28884 New encoding, targeting Xpulpv2 now 2016-05-10 17:45:57 +02:00
Andreas Traber
d548ea579e Add sleeping bit to debug register 2016-05-06 17:29:22 +02:00