All functions in simutil_verilator return booleans to indicate
success/failure, where 1 == true, and 0 == false.
simutil_verilator_set_mem() returns an int due to DPI interface
restrictions. Before, 0 meant success, and 1 meant error.
To keep things nice and consistent, turn things around and align with
the bool meaning.
Support initialization of memory by loading content from ELF files.
All segments of the ELF file with the type `PT_LOAD` are merged into a
temporary buffer and then forwarded to a predefined memory.
This is an addition for setting the memories with VMEM files.
Memories must implement `simutil_verilator_set_mem` to support the
setting of values with a width of 32 bits. A return value of 0 must
indicate a successful operation and 1 an error.
Memories are defined by a call to `RegisterMemoryArea()` before the
execution of the simulation, at which point the arguments are parsed and
the initialization is started. The memories are identified by unique
name. The design specific location is used to set the SystemVerilog
scope.
Registered memories can be printed by using `-l list`. The unique name
is used for `-l name,file.elf` together with the file path.
An optional part of the argument is the type of the file, `elf` or
`vmem`, and if not provided it is attempted to detect the type by
looking at the file extension.
The memory specific arguments which already existed accept now also ELF
files. They use predefined names and are included to keep the interface
stable.
Contents of an ELF segment which has a bigger memory size than file size
are not set. This is typically required for BSS sections for zero-ing
the memory.
- Switch from Makefile calling fusesoc to fusesoc calling Makefile
- Pass parameters through DPI rather than as env variables
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Instead of copying the commands from the documentation or using the
shell history to find the commands use a Makefile as a convenience to
run some common tasks.
A shell's completion system can make use of the targets and provide tab
completion.
In debug mode, exceptions shall not update any CSRs including `mcause`,
`mepc`, `mtval`, `dpc` and `mstatus`, see Debug Spec v0.13.2, p.39.
This resolveslowRISC/ibex#168.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
All CSR addresses supported by the TB are now delared as an X
macro list. This list is then used to autogenerate the enum
type, string print helper and an array of all addresses.
The array of addresses can now be used by the randomize generator
to turn an arbitrary integer index into an address. This removes
the restriction on only generating contiguous address ranges noted
in #443.
Add missing signal csr_restore_dtret_i
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit removes a copy of the dummy clock gating primitive from
tree previously used for UVM-based DV. There is another, identical copy
of the same primitive in `shared/rtl` that can be used instead.
This resolveslowRISC/ibex#213.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit modifies the assertions to not fire as long as the reset
is active. Also, it updates some assertions.
This resolveslowRISC/ibex#274.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Move Xilinx specific code into shared folder so it can be re-used by
different examples.
Use the shared RAM code and make use of byte enable signal.
Fixeslowrisc/ibex#144
This commit reworks the generation of the `core_busy` signal used to
control the main clock gate of the core. Without this commit, the
controller generates a separate `first_fetch` signal only asserted in
the FIRST_FETCH state that directly controls `core_busy` and thus the
main clock gate. This is problematic as it introduces a feedback to
from the controller state into the clock.
This commit removes the problematic signal and changes the generation of
`ctrl_busy` in the FIRST_FETCH state of the controller. This signal is
now used to control the main clock gate in all states (previously all
except FIRST_FETCH) but it gets registered, thus it does not introduce
the feedback into the clock.
This resolveslowRISC/ibex#211.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit removes a redundant for `ebrk_insn` in the `DBG_TAKEN_ID`
state. If this signal is not set, the controller does not enter this
state in the first place. This is not changing functional behavior,
but removes a `MISSING_ELSE` coverage hole reported by @udinator.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit turns the last case in the exception handling if/else block
from an `else if` to an `else`. This is not changing functional
behavior as the same condition is checked previously, but removes a
`MISSING_ELSE` coverage hole reported by @udinator.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Without this commit, writes to `dpc` with the LSB set are completely
ignored. This commit changes the implementation to ignore the LSB only.
This is the same behavior as seen required for `mepc`. This resolves
lowRISC/ibex#444.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit reworks the code section describing how the performance
counter CSRs are accessed by CSR instructions. Instead of using an
address mask inside the default case, and excluding CSRs in the same
address range previously handled (like `mcycle(h)`, `minstret(h)`,
`mcountinhibit`), all performance counter CSRs are now explicitly
enumerated. This enhances readability of the code and enhances
compatibility with some tools without changing behavior or causing
lint problems.
This commit is based on suggestions from @MarekPikula. It replaces the
proposal in lowRISC/ibex#336.
Simple system is a basic verilator top-level testbench for running
executables. It has functionality for outputting text to a log file
and for the software to terminate the simulation
