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Author SHA1 Message Date
udinator
edf9371c6c
[DV] Increase number of resets in reset_test (#418) 2019-10-25 14:28:06 -07:00
udinator
d3c7b887d7
[DV] Increase number of illegal instructions generated (#426) 2019-10-25 14:00:22 -07:00
Pirmin Vogel
0331ed61b1 [rtl/alu] Remove unused comparison operations 
These operations (ALU_GT, ALU_GTU, ALU_LE, ALU_LEU) are remnants of
of the original OpenRISC design. RISC-V does not have these instructions
and instead implements the operations by reversing operands for ALU_LT,
ALU_LTU, ALU_GE, ALU_GEU.

This resolves lowRISC/ibex#420 reported by @udinator.
 2019-10-25 13:58:59 +01:00
Marek Pikuła
294849bb18 [RTL] Add MultiplierImplementation parameter in top level 2019-10-24 14:33:24 +01:00
udinator
c89e431937
Update google_riscv-dv to google/riscv-dv@46ec4bc (#417) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 46ec4bc48bc1eebc5a2bcd48fe4ce4c77105fead

* Incorrect deletion (google/riscv-dv#249) (eroom)
* Updated OVPsim log processing for coverage (google/riscv-dv#248)
  (eroom)
* Improve illegal/hint test coverage (google/riscv-dv#247) (taoliug)
* Coverage model fixes (google/riscv-dv#246) (taoliug)
* Add back-to-back jump instruction test (google/riscv-dv#244)
  (taoliug)
* Functional coverage improvement (google/riscv-dv#243) (taoliug)
* Functional coverage improvement (google/riscv-dv#242) (taoliug)
* Support c.jr,c.jalr, fix coverage sampling issues (google/riscv-
  dv#241) (taoliug)
* allow select a random GPR for JALR op (google/riscv-dv#240)
  (taoliug)
* Fix coverage definition/sampling issue (google/riscv-dv#239)
  (taoliug)
* Testlist clean up, add RV32I target (google/riscv-dv#238) (taoliug)
* Consolidate the coverage collection script (google/riscv-dv#234)
  (taoliug)
* Fixed default values, and trailing blank lines (google/riscv-dv#233)
  (eroom)
* Refine README structure (google/riscv-dv#231) (taoliug)
* Add pre-defined target: RV32IMC, RV64IMC (google/riscv-dv#230)
  (taoliug)
 2019-10-23 10:46:31 -07:00
udinator
023b7b6856
[RTL/Tracer] Fix compressed jump RD write (#416) 2019-10-23 10:30:11 -07:00
udinator
8e40f65582
[DV] Enable timer interrupts (#415) 2019-10-23 09:33:50 -07:00
Tobias Wölfel
0728fb7e9f [DV] Update simulation terminate argument 
Add description to usage output.
Add short option '-c'.
 2019-10-21 22:19:24 +02:00
udinator
c808fed7d1
[DV] testplan documentation (#409) 2019-10-21 11:45:40 -07:00
udinator
beb40d89f6
[DV] Add interrupt wfi test to address coverage hole (#410) 2019-10-21 11:44:23 -07:00
Philipp Wagner
1c3903e2ce Tracer: Decode an all-zero instruction as c.unimp 
Fixes #396
 2019-10-17 13:48:29 +01:00
Greg Chadwick
edb33cca56 Add Greg Chadwick to CREDITS.md 2019-10-17 11:07:05 +01:00
Greg Chadwick
6b1a7add5d [Doc] Added extra setup info for Verification 2019-10-17 10:31:18 +01:00
udinator
b2e36ec345
Update google_riscv-dv to google/riscv-dv@033fccf (#406) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 033fccfbd50f6412e66b448a1d04245d787004bd

* Add more ebreak generation control (google/riscv-dv#229) (udinator)
* Fix timemout, misc update to README (google/riscv-dv#228) (taoliug)
* Fix CSR test setup (Udi)
* Update spike setup instruction for commit log (google/riscv-dv#226)
  (taoliug)
* Fix spike arguments to generate commit log (google/riscv-dv#225)
  (Greg Chadwick)
* Minor README typo (google/riscv-dv#219) (Dan Petrisko)
* Add random FCSR programing, add RV32FC/DC support (google/riscv-
  dv#221) (taoliug)
* Add floating point load/store support (google/riscv-dv#220)
  (taoliug)
* Fix floating point comparison issue (google/riscv-dv#218) (taoliug)
* Add basic support for F/D extension (google/riscv-dv#217) (taoliug)
* Generate the ucdb file inside output directory (google/riscv-dv#215)
  (Hai Hoang Dang)
* cov.py: Allow coverage to run with different simulator
  (google/riscv-dv#214) (Hai Hoang Dang)
 2019-10-16 17:50:23 -07:00
udinator
fc80203af3
[DV] Debug_ebreak test fix (#405) 2019-10-16 17:44:47 -07:00
taoliug
1b71320230
Add RV32IM test (#404) 2019-10-16 10:15:49 -07:00
Philipp Wagner
59fdbb517f Licensing documentation: Add commercial support info 
lowRISC provides commercial support for Ibex, mention that in the
licensing page if people are looking for such an offering.

Can be extended in the future as we know of more companies offering
support.
 2019-10-16 15:08:45 +01:00
Philipp Wagner
2cc282aeee Improve copyright/licensing page 
Rename the page to "Licensing", and improve its contents to be more
helpful to people not familiar with open source projects and the Apache
license.
 2019-10-16 15:08:45 +01:00
Greg Chadwick
cc94bc8d54 [RTL] Fix single stepping on exceptions 
When we single step over an instruction that causes an exception DPC
should be set to point to the exception handler (where we would have
gone were we not single stepping).
 2019-10-16 10:23:05 +01:00
Greg Chadwick
b94961402c [RTL] Fix ebreak behaviour in U-mode 
Fixes #370

Whether EBREAK enters debug mode is controlled by the
ebreaku and ebreakm dcsr fields. Which is relevant depends upon the
privilege level.
 2019-10-16 09:10:34 +01:00
Greg Chadwick
7aa87156d3 [RTL] Fix ebreak and cleanup debug 
Fixes #393

When entering debug mode in controller need to ensure ID doesn't get
flushed until the relevant debug state can see the contents of ID and
perform the appropriate actions. ID is flushed at that point.

Also cleaned up some code replication around entering debug mode
(debug_req vs single step look very similar so can use the same code
paths).
 2019-10-16 09:10:34 +01:00
udinator
6b8b3762ec
[DV] Fix bugs in mem_error test to circumvent test deadlock (#400) 2019-10-15 15:19:36 -07:00
Greg Chadwick
2bc785e7d9 [RTL] Prevent CSR write on any illegal CSR reason 
Debug register access sets illegal_csr if not in debug mode but CSR
write still went ahead. This modifies the CSR write to ensure that
anything that results in an illegal CSR instruction being signalled will
prevent a CSR write.
 2019-10-15 14:43:55 +01:00
udinator
bbb688a2aa
[DV] Fix lint warnings (#397) 2019-10-14 10:20:28 -07:00
Pirmin Vogel
5f0be50473 Remove non-ASCII characters from .sv and .rst files 2019-10-14 09:08:16 +01:00
udinator
5972c63ba8
[DV] Let time-consuming checker tasks detect failures (#395) 2019-10-11 13:48:20 -07:00
udinator
ae82d61401
[DV] Add reset test (#392) 2019-10-10 13:01:32 -07:00
udinator
2ca1a6da21
[DV] Update csr description for U-mode changes (#387) 2019-10-10 09:18:48 -07:00
udinator
566e73c352
[RTL] Enable reading mstatus.tw (#388) 2019-10-10 09:17:14 -07:00
Alex Bradbury
0abe5ccaf7 [CI] Stop pinning an old attrs version 
simplesat (required by fusesoc) was broken by an update to the attrs
library. Now simplesat 0.8.2 has been released which fixes the issue, we
can remove the explicit pinning of the old attrs version.
 2019-10-10 16:22:56 +01:00
Philipp Wagner
2b6a95190e Remove outdated waiver 
With the introduction of U mode this signal is always read.
 2019-10-09 13:35:01 +01:00
Philipp Wagner
3db46f91e0 Tie off csr_pmp_* signals for all lint tools 
Our generic way of marking signals as unused is assigning them to an
unused_* signal. That works for all lint tools and avoids tool-specific
waivers.
 2019-10-09 13:35:01 +01:00
Philipp Wagner
90ff45abbd Avoid self-determined bit length of signals 
This works around a lint error we get; the old and the new version are
equally wrong or right, but it doesn't seem to be worth fighting with a tool.
 2019-10-09 13:35:01 +01:00
Philipp Wagner
cdc8078c0f ibex_cs_registers: Add missing generate name 
One condition is missing a generate label.
 2019-10-09 13:35:01 +01:00
Tom Roberts
c33525ae80 [RTL LSU] Change unaligned error behaviour 
- If an error is signalled in the first part of an unaligned
  transaction, the second part is issued anyway (to avoid a
  timing loop from data_err_i -> data_req_o)
- Previously, the error was signalled and an exception was taken
  as soon as the first transaction completed. This commits makes
  the core wait until both transactions have completed.
- This prevents strange behaviour caused by the lsu and controller
  being out of sync (fixes #374).
 2019-10-09 10:07:07 +01:00
udinator
4a1806f16f
Update google_riscv-dv to google/riscv-dv@ad6fe56 (#385) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision ad6fe565a91445cc3ea3e32119360b57af4f19b2

* Workaround for dsim compile issue (google/riscv-dv#211) (taoliug)
* Add a --seed_yaml option to rerun a regression with the same seed of
  a prior regression (google/riscv-dv#210) (taoliug)
* Update questa covearge options (google/riscv-dv#209) (taoliug)
* Fix disable_compressed_instr option (google/riscv-dv#205) (taoliug)
* Fix non-compressed instruction test (google/riscv-dv#203) (taoliug)
* Debug single step functionality and config knobs (Udi)
* Fix no_branch_jump option (google/riscv-dv#200) (taoliug)
* Add more functional covergroup (google/riscv-dv#199) (taoliug)
* Allow randomly reserve GPR for TP/SP, improve functional coverage
  (google/riscv-dv#198) (taoliug)
* Allow running the coverage script with LSF (google/riscv-dv#195)
  (taoliug)
* Add support for disable_compressed_instr (google/riscv-dv#194)
  (taoliug)
* Improve coverage collection performance (google/riscv-dv#193)
  (taoliug)
* Signature_addr_reg constraint update (Udi)
* Add a debug mode for functional coverage (google/riscv-dv#191)
  (taoliug)
* Fix typo in README (google/riscv-dv#189) (taoliug)
* Constrain scratch_reg (google/riscv-dv#188) (udinator)
* Update README for the coverage flow (google/riscv-dv#187) (taoliug)
* Add basic privileged CSR cover group (google/riscv-dv#186) (taoliug)
* Fix cover point definition (google/riscv-dv#185) (taoliug)
* Fix ovpsim log compare issue (google/riscv-dv#183) (udinator)
 2019-10-08 14:22:05 -07:00
udinator
9824342c03
[DV] Added unaligned memory error test (#378) 2019-10-08 09:31:49 -07:00
Tobias Wölfel
912d6da1c2 Update description for running RISC-V compliance 
The RISC-V compliance test system requires an absolute path to the
executable or one which starts at `riscv-test-suite/*`.
 2019-10-08 15:22:37 +02:00
Tobias Wölfel
73224d9c51 Remove reference to simulation 
The testbench does not exist anymore.
 2019-10-08 11:57:19 +02:00
Philipp Wagner
ee1098f9af Tracer: Reference Verilator bug for miscompilation 
This miscompilation is now reported and fixed, mention it in the code to
refer back to it when we can revert back to the old code (which will
take a couple months until we can require a newer Verilator version).

Fixes #372
 2019-10-06 12:55:59 +01:00
Philipp Wagner
d8e4852f76 Include rs1 and rd in trace of c.addi16sp 
New output looks like this:

118         55      00000154        6121    c.addi16sp      x2,64     x2:0x00000030  x2=0x00000070

Fixes #322
 2019-10-05 18:22:14 +01:00
udinator
84664077ee
[DV] Top level toggle coverage (#371) 2019-10-04 16:36:47 -07:00
Greg Chadwick
b1a0cac126 [Doc] Add more pipeline details 2019-10-04 11:36:24 +01:00
Greg Chadwick
29d66a7fa4 [Doc] Fix for table wrapping in RTD theme 
This causes wide tables to wrap content within their cells rather than
producing a table with a scroll bar see
https://github.com/readthedocs/sphinx_rtd_theme/issues/117 for details.
 2019-10-04 11:36:24 +01:00
Philipp Wagner
2acb497d22 Add missing enum cast 
Vivado doesn't compile the design without this cast.
 2019-10-03 16:56:26 +01:00
Tom Roberts
6aae5fe975 [Doc] Fix some rendering issues in cs_registers 
- fixes #306
 2019-10-03 10:41:29 +01:00
Tom Roberts
f35db04b7c [RTL PMP] Fix address matching bugs 
- Partial matching not relevant for 32bit only accesses
- Apply region size masking correctly
 2019-10-03 10:41:29 +01:00
Tom Roberts
2aacd2b98b [Priv modes] Add support for U-Mode 
- General changes to suport U-mode (fixes #88)
- Update documentation
- Add priv mode flops to CSRs module
- Propagate correct priv mode to PMP module
- Implement CSR priv-mode permission checking
- Implement illegal U-mode instruction checking
- Add extra mstatus bits for U-mode (MPRV and TW)
 2019-10-03 10:41:29 +01:00
Philipp Wagner
f54dfe5d4b RISC-V Compliance test: Enable tracing 
Use the tracing-enabled core wrapper when executing the RISC-V
compliance test suite to help with debugging it.
 2019-10-03 09:42:45 +01:00
udinator
48e604ab9e
[DV] Update ibex log regex (#366) 2019-10-02 13:16:47 -07:00