The register is redundant to the PLIC in pulpissimo and is never written by the PULP_SDK.
Therefore enable all Interrupts from the beginning to ensure functionality.
This commit adds 32 non-standard, custom, fast interrupts to Ibex. These
interrupts are managed via 3 custom CSRs: `miex`, `mipx` and `mtvecx`.
`mtvecx` is initialized just like `mtvec`. Upon handling such a custom
interrupt, the core uses two signals (ACK + ID) to inform a possible
platform-level interrupt controller accordingly.
The purpose of adding these non-standard interrupts is to have an
interrupt framework compatible with RI5CY/CV32E40P for platforms that can
use the two cores interchangeably (PULP/PULPissmio).
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit replaces the generic `prim_clock_gating` cell with the
`cluster_clock_gating` cell used in PULPissimo.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit modifies the encoding of SROI, RORI, SBEXTI, GREVI and GORCI by
forcing Bit 26 to zero to prevent overlapping encodings with FSRI.
The bitmanip draft spec doesn't explicitly state that Bit 26 for those
instructions must be zero. However, those instructions only ever use
log2(XLEN) LSBs of the immediate. This means they don't use Bit 26 in RV32.
Instead, whenever Bit 26 is set, these instructions are instead decoded as
FSRI.
The parameters are not used as the instructions are not yet widely
supported.
Keep definitions so they can be easily activated later.
Tracked in issue lowrisc/ibex#1228
Xcelium 19.03 doesn't support the `->` (binary logical) operator, but
using `|->` (overlapping implication) is equivalent here and supported;
use this operator instead.
Fixes#1213
These changes correspond to similar changes in the prefetch buffer to
support branch prediction. A registered version of fill_ext_done was
required to prevent a combinational loop from branch_i in to valid_o
out.
Multiplexing priorities for fifo_addr have been swapped to match
fetch_addr_d in the same module and all similar multiplexing in the
icache (prioritize incoming branch_i over branch_mispredict_i). Note
however that it is not expected that these conditions will actually
occur together, and an assertion has been added to check that.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Remove the SpeculativeRequest parameter, and replace it with a
policy. If the cache is disabled, make the request on the basis that we
definitely won't hit in the cache and so should make the bus request
asap.
Stop fill buffers from fetching complete cache lines when the cache is
disabled. When the core branches into the middle of a line, the lower
words would normally be fetched to complete the line. This is
unnecessary when the cache is disabled since those words will just be
thrown away and the core will stall while they are being fetched.
These two changes make the performance using the disabled icache the
same as using non-icache prefetch buffer.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Make sure performance counters only count retired, non-trapping
instructions excluding ebrk/ecall
- Rewire some signalling through the writeback stage to allow
instruction retire to be signalled from one place
- Relates to #1132
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Reduce the size of the PMP address configuration registers to the
permissible minimum depending on granularity.
- Ensure consistency between PMP address CSR reads and the addresses
forwarded to the PMP module.
- Follow the specification more strictly, by returning bits
pmpaddr[G-2:0] as all ones when pmpcfg.A[1] is set (i.e. mode is
NAPOT or NA4, though the latter is invalid for G > 0) and bits
pmpaddr[G-1:0] as all zeros when pmpcfg.A[0] is clear (i.e. mode is
OFF or TOR).
- Fixes#1181
- Generate correct masks for NAPOT range addresses covering the entire
granule. When PMPGranularity > 0, then a NAPOT range can span the
whole granule, which requires the next-lowest bit (i.e. highest bit
that is not part of the granule) to be 0.
- Fixes#1178
This PR makes changes to support Cadence Xcelium 20.09.001
Compile error 1: Fixed the following rtl compile error in ibex_cs_registers.sv
assign tselect_rdata = {'b0, tselect_q};
|
xmvlog: *E,NONOWD (/proj/riscv_ibex/users/paulok/lowRISC/ibex_1/rtl/ibex_cs_registers.sv,1288|30): Illegal use of a constant without an explicit width specification [4.1.14(IEEE)].
Compile error 2: Fixed the following DV compile error in ibex_mem_intf.sv
.data_req_o (data_mem_vif.request ),
|
xmelab: *E,ICDCBA (./tb/core_ibex_tb_top.sv,89|14): Illegal combination of driver and output clockvar to variable 'request' detected (output clockvar found in clocking block at line 25 in file ./common/ibex_mem_intf_agent/ibex_mem_intf.sv).
Simulation probes: Fixed issue with probing in yaml for xrun and added licqueue.
Signed-off-by: Paul OKeeffe <paul_okeeffe@crevinn.com>
Fix two Verilator lint warnings if icache is used. The branch predictor
is currently only used together with the prefetch buffer, and those
signals are unused in the icache configuration.
- Move various unused signal fixes from the waiver file to the rtl, so
that all tools can pick them up.
- Fix some oversize line issues.
- Fix some signed / unsigned casting issues.
- Remove some extraneous semicolons.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Add parameter `DbgHwBreakNum` to configure the number of HW breakpoints.
The parameters controls the number of trigger registers available if
debug support is enabled with `DbgTriggerEn`.
Closes#1070
- This field is read-only to software, and so should retain its previous
value on a write. This fixes#1134.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- This change should have no functional impact on the design
- Adding the separate module will allow easy parameterization
of security hardening for individual CSRs in the future
- As a side benefit, clock gating is added for CSRs that didn't
previously have it
- Note that this change makes the cpuctrl register always present,
rather than individual bits being added depending on parameterized
features. This is not ideal, but the parameterization becomes rather
messy otherwise.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Document that SecureIbex cannot be used without a multiplier and add
an assertion in the rtl. This fixes#1080.
- Move the PC checking hardware onto its own parameter to match all the
other individual security features.
- Make the PC increment behavior more sensible on fetch errors (and make
it match the icache behavior). Factor this into the PC increment check
to prevent false triggering, fixes#1094.
- Stop the PC mismatch checker firing on dummy instructions, fixes
#1095.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Without the B extension, a gorci instruction should decode as an
illegal instruction.
- Relates to #1129
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Option to control the state of the Ibex tracer.
Defaults to enable, but allows a setting to disable the trace log.
In long running simulations this file can get quite big and the contents
might not be needed. Use the argument `+ibex_tracer_enable=0` to prevent
the creation of the file.
At some point in the future, the version of binutils we're using, and
the released version of LLVM, will coincide to use the correct name. In
the meantime, this change just uses the number which is supported by
both compilers.
This is, as I understand it, the only stumbling block to compiling the
in-repo C benchmark code with both GCC and LLVM. Being able to do so
would make it much easier for us to do comparisons on the benchmarks for
both compilers.
Signed-off-by: Sam Elliott <selliott@lowrisc.org>
Check that the number of cycles are always as specified for the current
configuration for data independent operations.
The required input signals for each arithmetic operation are split into
different files which are included into the testbench.
For each combination of operation and configured configuration
(slow/fast/single) a define stores the number of cycles in a separate
file. A target exists for each combination.
For a convenient execution the targets are grouped together in a
makefile.
The implementation is based on the formal/icache checks.
For the selection of the single cycle multiplication with the fast
multiplication the parameter is set directly to the enum integer value.
- If there is a request to enter debug mode (either due to a halt
request or single stepping mode) on the same cycle as an EBREAK
instruction, continue with the EBREAK and capture the ID PC rather
than the IF PC.
- relates to #1106
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- The core does not rely on instr_err_i being always valid, and most bus
protocols don't support that
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Currently in ibex_controller.sv when generating the ID of any fast
interrupts, irq_fast[5] is checked for twice.
This is a redundant line, and so this PR simply removes it.
Signed-off-by: Udi <udij@google.com>
This commit replaces the previous combination of `RV32M` bit parameter
used to en/disable the M extension and the `MultiplierImplementation`
used to select the multiplier implementation by a single enum parameter.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This signal aimed to ensure loads/stores completed succesfully when an
interrupt or debug request appeared at the same time they were being
executed when the writeback stage is present. However other stall logic
suffices for this purpose (debug/interrupt will wait for instruction to
unstall in ID/EX which only happens once request has been sent out, then
first instruction of debug/interrupt handler will stall until load/store
response has been seen based on the generic stall logic for lsu requests
in the writeback stage).
With this signal in place debug single stepping was broken around loads
and stores.
Fixes#1029
Previously, these bits were not checked when decoding slli, srli and
srai, causing some illegal instruction encodings not to trigger an
illegal instructions exception.
This resolveslowRISC/Ibex#1018.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- Add SECDED ECC checking to the register file when SecureIbex is
enabled
- No correction is attempted, but an alert is raised for the system to
intervene
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Add a major and minor alert output which can be used by the system to
react to fault injection attacks
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
