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cvxif/2021/v0.1

cvxif/2022/v0.2

dependabot/pip/doc/jinja2-3.1.3

dvsim_report

gh-readonly-queue/master/pr-2051-90ee203a9a44773061e824711d281d2c3557a200

gsoc/2020/pointer-authentication

harryc_ci_test

marnovandermaas-patch-1

master

pmp-coverage-improvement

pmp_ci_run_and_cov_merge_fixes

pmp_cov_test

pulpinov1

pulpissimo

revert-2226-fix_counter_reset_value

riscv-formal

rtl_log_fix

test_csr_cov_improvements

upd_directed_test_flow

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pulpino-v1.0.0

pulpissimo-v1.0

pulpissimo-v1.0.0

pulpissimo-v1.0.1

pulpissimo-v4.1.0

pulpissimo-v6.0.0

pulpissimo-v6.1.0

pulpissimo-v6.1.1

3b9f5e83b0

Merge c15202c96d into 594ea976c9 Akilesh Kannan 2025-04-20 16:08:12 +00:00
c15202c96d

lint: verilator lint fixes for regfile common security module Akilesh Kannan 2025-04-20 21:38:04 +05:30
912c251185

Add common register file module to build targets Akilesh Kannan 2025-04-20 09:35:09 +05:30
669b130637

[rtl] use common security module in all three regfile implementations Akilesh Kannan 2025-04-20 09:20:02 +05:30
8466e42a9c

[rtl] Add common security features of regfiles to separate module Akilesh Kannan 2025-04-19 22:21:42 +05:30
c3d0503790

Merge d50fe2585a into 594ea976c9 Marno van der Maas 2025-04-03 12:10:29 +00:00
9e5caabea5

Merge a3865e6cd0 into 594ea976c9 Robert Schilling 2025-04-03 12:10:29 +00:00
bebf80db82

Merge 49ae3fdfc4 into 594ea976c9 dependabot[bot] 2025-04-03 12:09:52 +00:00
be25042489

Merge c548445f67 into 594ea976c9 Canberk Topal 2025-04-03 12:09:37 +00:00
1c0362a11a

Merge 2665328947 into 594ea976c9 leesum 2025-04-03 12:09:33 +00:00
60a9881636

Merge 5aaa9f6292 into 594ea976c9 Asim Ahsan 2025-04-03 12:09:33 +00:00
b3975560d4

Merge f4ed1425a3 into 594ea976c9 Pirmin Vogel 2025-04-03 12:09:29 +00:00
7fb2c5e0c5

Merge 7fc35aba8a into 594ea976c9 Saad Khalid 2025-04-03 12:09:26 +00:00
47e38c569d

Merge e338d61823 into 594ea976c9 Saad Khalid 2025-04-03 12:09:26 +00:00
9a83c4df27

Merge da76b69300 into 594ea976c9 Saad Khalid 2025-04-03 12:08:43 +00:00
333f7ea7c3

Merge c79aac0b62 into 594ea976c9 Abdul Wadood 2025-04-03 12:08:36 +00:00
9416616d4f

Merge 792f6a96e4 into 594ea976c9 TrellixVulnTeam 2025-04-03 12:08:15 +00:00
29e47eeb15

Merge 91cc057f5e into 594ea976c9 Andreas Kurth 2025-04-03 12:08:10 +00:00
e1490353d4

Merge 599cb5f261 into 594ea976c9 Neeraj Krishnan Kalathara 2025-04-03 12:07:57 +00:00
00ee478e94

Merge b32c31bb93 into 594ea976c9 Haseeb Azaz Talib 2025-04-03 12:04:55 +00:00
3c9b638cef

Merge 77aaf7db9e into 594ea976c9 Stefan Wallentowitz 2025-04-03 12:02:20 +00:00
594ea976c9 [dv] Plan test for DM accesses in debug mode master Andreas Kurth 2025-03-28 07:45:27 +01:00
9540548ffd [dv] Plan test for DM accesses in debug mode Andreas Kurth 2025-03-28 07:45:27 +01:00
2678654820 fix: Illegal instruction display message Hao 2025-03-26 09:32:24 +08:00
f92d61c77c

fix: Illegal instruction display message Hao 2025-03-26 09:32:24 +08:00
6e466c1504 Verification should be done with ibex_cosim branch Marno van der Maas 2025-02-21 16:41:22 +00:00
100f1eb8b1

Verification should be done with ibex_cosim branch marnovandermaas-patch-1 Marno van der Maas 2025-02-21 16:41:22 +00:00
9e99ec79e2 [ci] switch CI runner from Ubuntu 20.04 to 22.04 Gary Guo 2025-02-19 13:35:45 +00:00
eba210965a [ci] update verible version to match OT Gary Guo 2025-02-19 13:43:59 +00:00
fa40368300 [ci] remove Azure Pipelines magic commands Gary Guo 2025-02-19 15:50:17 +00:00
fe837acc81 [ci] switch CI runner from Ubuntu 20.04 to 22.04 Gary Guo 2025-02-19 13:35:45 +00:00
7ee46a7292 [ci] update verible version to match OT Gary Guo 2025-02-19 13:43:59 +00:00
db332745de [ci] remove Azure Pipelines magic commands Gary Guo 2025-02-19 15:50:17 +00:00
60fbb6ba2f [cosim] Update comment on set_mip in Cosim interface Greg Chadwick 2025-02-14 15:44:36 +00:00
d53035bf64 [rtl] Remove low utility assertions Greg Chadwick 2025-02-14 10:01:22 +00:00
0f27580cf6 [rtl] Flush pipe on all CSR modifications Greg Chadwick 2024-09-17 13:51:01 +01:00
e66df4d49a [rtl] Read csr_addr direct from instruction Greg Chadwick 2025-02-14 13:41:26 +00:00
866572c130 [rtl] Flush pipe on all CSR modifications Greg Chadwick 2024-09-17 13:51:01 +01:00
1e4789a255 [rtl] Read csr_addr direct from instruction Greg Chadwick 2025-02-14 13:41:26 +00:00
32f3863ac8 [cosim] Update comment on set_mip in Cosim interface Greg Chadwick 2025-02-14 15:44:36 +00:00
2bb3fc7be4 [rtl] Remove low utility assertions Greg Chadwick 2025-02-14 10:01:22 +00:00
a3865e6cd0 [ibex,tracer] Uniquify trace log with module hierarchy Robert Schilling 2025-02-14 09:18:18 +01:00
d50fe2585a Formal: Lint fixup Marno van der Maas 2025-01-13 13:51:02 +00:00
e952ccbe30 Formal README revision Marno van der Maas 2024-09-17 14:56:43 +01:00
3ef74938af Use Nix to setup formal development and test environment Harry Callahan 2024-08-06 22:57:43 +01:00
c525a90fbb Add a fusesoc flow to dv/formal for generating the fileset Harry Callahan 2024-08-09 13:01:35 +01:00
82a142b14c Formal equivalence checking with Sail Louis-Emile 2024-06-26 10:14:58 +01:00
78739562ce [ibex_core] Fix assertion when SecureIbex is false Rupert Swarbrick 2025-01-23 18:45:18 +00:00
cecf4fd2df [ibex_register_file_fpga] Drop two confusing comments Rupert Swarbrick 2025-01-23 18:35:28 +00:00
8500fc5f26 [ibex_core] Fix assertion when SecureIbex is false Rupert Swarbrick 2025-01-23 18:45:18 +00:00
aff062d0ca [ibex_register_file_fpga] Drop two confusing comments Rupert Swarbrick 2025-01-23 18:35:28 +00:00
591c3812f9 Fix typo in comment in ibex_id_stage.sv Katharina 2025-01-16 17:54:41 +01:00
7e0a9a3262

Fix typo in comment in ibex_id_stage.sv Katharina 2025-01-16 17:54:41 +01:00
bf244d5276 ibex_simple_system_cosim.core : c++11 -> c++14 Harry Callahan 2025-01-13 15:40:22 +00:00
5da1679f36 [ibex_tracer] Use static variables in always/final blocks Robert Schilling 2025-01-09 20:34:42 +01:00
0124aa48b2 [ibex_tracer] Use static variables in always/final blocks Robert Schilling 2025-01-09 20:34:42 +01:00
4d722d3308 [rtl] Drive oh_raddr_*_err if RdataMuxCheck=0 Rupert Swarbrick 2025-01-06 17:09:19 +00:00
e5be77accf [rtl] Drive oh_raddr_*_err if RdataMuxCheck=0 Rupert Swarbrick 2025-01-06 17:09:19 +00:00
6372c810b0

fix: compressed decoder Hao 2025-01-06 12:30:23 +08:00
599cb5f261

Merge branch 'master' into master Neeraj Krishnan Kalathara 2025-01-01 14:00:32 +05:30
8f4c75c5e4 Update core_ibex_pmp_fcov_if.sv Priyanshu Mishra 2024-12-20 16:12:27 +05:30
16e947e20b

Update core_ibex_pmp_fcov_if.sv Priyanshu Mishra 2024-12-20 16:12:27 +05:30
a05d4d825c [rtl,pmp] Allow all accesses to Debug Module in debug mode Andreas Kurth 2024-12-13 13:51:30 +00:00
8b82e89719 [controller] Add assertion on pipeline flush when entering debug mode Andreas Kurth 2024-12-16 11:22:28 +00:00
88d27a0944 ibex_pcounts: resolve uninitialize warning Marno van der Maas 2024-11-27 16:42:46 +00:00
68f1a9fb1b [rtl,pmp] Allow all accesses to Debug Module in debug mode Andreas Kurth 2024-12-13 13:51:30 +00:00
fe2226ce57 [controller] Add assertion on pipeline flush when entering debug mode Andreas Kurth 2024-12-16 11:22:28 +00:00
667fd20d2e [rtl] Fix non-DSP reset in ibex_counter Pascal Nasahl 2024-11-29 18:58:35 +01:00
83696ecc22 [rtl] Fix non-DSP reset in ibex_counter Pascal Nasahl 2024-11-29 18:58:35 +01:00
0945aa84c6 Revert "[rtl] Fix counter reset value on FPGA" Pascal Nasahl 2024-12-02 16:05:24 +01:00
b30abd4eb2

Revert "[rtl] Fix counter reset value on FPGA" revert-2226-fix_counter_reset_value Pascal Nasahl 2024-12-02 16:05:24 +01:00
54985d21b0 [rtl] Fix counter reset value on FPGA Pascal Nasahl 2024-11-27 15:28:06 +01:00
3428e0cdf9 [rtl] Fix counter reset value on FPGA Pascal Nasahl 2024-11-27 15:28:06 +01:00
7f71ba1644 ibex_pcounts: resolve uninitialize warning Marno van der Maas 2024-11-27 16:42:46 +00:00
d2d55ed348 [ci] remove Azure Pipelines Gary Guo 2024-11-22 16:06:23 +00:00
f6dc71534e [ci] remove Azure Pipelines Gary Guo 2024-11-22 16:06:23 +00:00
84232a5bfa [rtl] Fix zero value in FPGA RF Pascal Nasahl 2024-11-18 12:45:35 +01:00
a38e37342c [rtl] Fix zero value in FPGA RF Pascal Nasahl 2024-11-18 12:45:35 +01:00
f0f6bfd79a Block diagram: make feature text readable Marno van der Maas 2024-11-12 11:30:56 +00:00
76dc3ae44c Block diagram: make feature text readable Marno van der Maas 2024-11-12 11:30:56 +00:00
496e06f659 Block diagram: fixes and improved looks Marno van der Maas 2024-11-08 14:44:31 +00:00
e3079eacbe Block diagram: fixes and improved looks Marno van der Maas 2024-11-08 14:44:31 +00:00
809ca511c4 Updating some issues in Makefile.tools SamuelM 2024-10-17 16:21:50 +03:00
fb49826c16 [dv] Cleanup some code in the compile_tb.py module Harry Callahan 2024-10-01 12:07:32 +01:00
8e77bb39d5 [dv] Tweak ISS linker arg construction for Xcelium Harry Callahan 2024-10-01 12:07:17 +01:00
c9660e5895 [dv] Cleanup some code in the compile_tb.py module Harry Callahan 2024-10-01 12:07:32 +01:00
eaed0da09c [dv] Tweak ISS linker arg construction for Xcelium Harry Callahan 2024-10-01 12:07:17 +01:00
5f4dc88377 refactored isolde/simple_system/Makefile daro 2024-10-01 09:33:38 +03:00
d49750a102 added new tests: dhrystone, fibonacci darotsr 2024-09-30 20:55:47 +03:00
52ea330cbb ibex_top is synthesisable darotsr 2024-09-30 17:00:48 +03:00
a7d4fc4680 first attemp to synthesis darotsr 2024-09-30 15:35:29 +03:00
e212b7dfed added tinyprintf in the SW darotsr 2024-09-29 21:30:53 +03:00
5f9e027763 new target, flist, for isolde/simple_system/Makefile darotsr 2024-09-29 17:33:23 +03:00
b44f01004a extended x register file with additional read ports daro 2024-09-24 13:23:37 +03:00
8ec6282ec8

Merge 00bec327a2 into f92d599e00 Harry Callahan 2024-09-24 09:23:59 +02:00
7755227294 improved rtl/isolde_exec_block.sv daro 2024-09-23 22:39:06 +03:00
1f3fa3045a NEW: instr encoding darotsr 2024-09-23 21:22:21 +03:00
b26686b3d3 refactored rtl/isolde_register_file_ff.sv daro 2024-09-23 10:47:01 +03:00
f92d599e00 [pmp] Use top-level straps for PMP reset values Robert Schilling 2024-03-01 17:42:07 +01:00
c199a74036 added rtl/isolde_exec_block.sv daro 2024-09-22 20:00:06 +03:00