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docs/datasheet
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Add a basic datasheet for RI5CY
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2015-09-09 18:35:07 +02:00 |
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include
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Cleanup tracer and defines
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2015-10-08 10:47:04 +02:00 |
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.gitignore
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Added vim swap file
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2015-07-24 15:26:32 +02:00 |
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alu.sv
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Remove some spaces
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2015-10-30 13:50:16 +01:00 |
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compressed_decoder.sv
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Update compressed decoder to RVC 1.9
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2015-10-27 12:39:59 +01:00 |
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controller.sv
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Fix debug breakpoints and single-step with branches in ID
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2015-10-29 14:12:50 +01:00 |
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cs_registers.sv
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Only read CSR when accessed
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2015-10-27 14:15:09 +01:00 |
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debug_unit.sv
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Add test_en to register file clock gates
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2015-10-28 12:47:33 +01:00 |
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decoder.sv
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Optimize stores: write data is passed through operand c, remove unneeded 32 bit register
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2015-10-02 15:03:49 +02:00 |
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ex_stage.sv
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Merge branch 'remove_vect'
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2015-10-18 19:57:42 +02:00 |
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exc_controller.sv
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Fix bug with hardware loops
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2015-10-25 19:26:46 +01:00 |
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hwloop_controller.sv
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Prefix all modules with riscv_ to avoid future conflicts
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2015-10-06 12:18:41 +02:00 |
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hwloop_regs.sv
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Prefix all modules with riscv_ to avoid future conflicts
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2015-10-06 12:18:41 +02:00 |
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id_stage.sv
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Add test_en to core and propagate it to manual clock gates
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2015-10-28 10:11:16 +01:00 |
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if_stage.sv
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Fix debug breakpoints (dbg_set_npc)
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2015-10-29 14:01:53 +01:00 |
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load_store_unit.sv
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Fix typo in last commit
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2015-10-16 14:34:33 +02:00 |
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mult.sv
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Merge branch 'remove_vect'
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2015-10-18 19:57:42 +02:00 |
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prefetch_buffer.sv
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Prefix all modules with riscv_ to avoid future conflicts
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2015-10-06 12:18:41 +02:00 |
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prefetch_L0_buffer.sv
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Prefix all modules with riscv_ to avoid future conflicts
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2015-10-06 12:18:41 +02:00 |
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register_file.sv
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Add test_en to register file clock gates
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2015-10-28 12:47:33 +01:00 |
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riscv_core.sv
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Fix debug breakpoints (dbg_set_npc)
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2015-10-29 14:01:53 +01:00 |
