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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
83 commits 21 branches 8 tags 70 MiB
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Andreas Traber 4baf8eaad9 Added missing compressed instruction: c.slt
2015-08-27 09:39:22 +02:00
include Eliminate pc_mux_boot 2015-08-25 15:37:26 +02:00
.gitignore Added vim swap file 2015-07-24 15:26:32 +02:00
alu.sv Updated all file headers 2015-07-24 15:26:12 +02:00
compressed_decoder.sv Added missing compressed instruction: c.slt 2015-08-27 09:39:22 +02:00
controller.sv Works, but bug in compressed decoder for sll 2015-08-26 22:57:49 +02:00
cs_registers.sv Move debug from CS registers to debug unit as they do not need to be 2015-08-14 16:31:03 +02:00
debug_unit.sv Move debug from CS registers to debug unit as they do not need to be 2015-08-14 16:31:03 +02:00
ex_stage.sv Remove dead signals 2015-08-17 15:19:48 +02:00
exc_controller.sv Updated all file headers 2015-07-24 15:26:12 +02:00
id_stage.sv Added missing compressed instruction: c.slt 2015-08-27 09:39:22 +02:00
if_stage.sv Works, but bug in compressed decoder for sll 2015-08-26 22:57:49 +02:00
instr_core_interface.sv Optimized IF intermediate step 2015-08-25 15:36:28 +02:00
load_store_unit.sv Updated all file headers 2015-07-24 15:26:12 +02:00
mult.sv Updated all file headers 2015-07-24 15:26:12 +02:00
register_file.sv Updated all file headers 2015-07-24 15:26:12 +02:00
riscv_core.sv Improve tracer output slightly 2015-08-27 01:11:34 +02:00
wb_stage.sv Remove dead signals 2015-08-17 15:19:48 +02:00