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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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| include | ||
| .gitignore | ||
| .gitlab-ci.yml | ||
| LICENSE | ||
| README.md | ||
| src_files.yml | ||
| zeroriscy_alu.sv | ||
| zeroriscy_compressed_decoder.sv | ||
| zeroriscy_controller.sv | ||
| zeroriscy_core.sv | ||
| zeroriscy_cs_registers.sv | ||
| zeroriscy_debug_unit.sv | ||
| zeroriscy_decoder.sv | ||
| zeroriscy_ex_block.sv | ||
| zeroriscy_fetch_fifo.sv | ||
| zeroriscy_id_stage.sv | ||
| zeroriscy_if_stage.sv | ||
| zeroriscy_int_controller.sv | ||
| zeroriscy_load_store_unit.sv | ||
| zeroriscy_multdiv_fast.sv | ||
| zeroriscy_multdiv_slow.sv | ||
| zeroriscy_prefetch_buffer.sv | ||
| zeroriscy_register_file.sv | ||
| zeroriscy_register_file_ff.sv | ||
| zeroriscy_tracer.sv | ||
zero-riscy: RISC-V Core
zero-riscy is a small 2-stage RISC-V core derived from RI5CY.
zero-riscy fully implements the RV32IMC instruction set and a minimal set of RISCV privileged v1.9 specifications.
In particular, zero-riscy supports the following machine-level CSR addresses: mhartid, mepc, mcause and the MIE/MPIE fields of the mstatus.
zero-riscy supports debug. The debug unit has been ported from RI5CY and it has the same specifications reported in http://www.pulp-platform.org/wp-content/uploads/2017/02/ri5cy_user_manual.pdf at page 26.
zero-riscy can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensios.
Roadmap for future features includes:
Supports for performance counters.