Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucorehardwarerisc-vrv32

Sven Stucki 96b5d1940d Fix issue with cross line access and stalls, cleanup		2015-08-25 15:36:28 +02:00
include	Simplify instruction masks in defines	2015-08-25 15:36:28 +02:00
.gitignore	Added vim swap file	2015-07-24 15:26:32 +02:00
alu.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
compressed_decoder.sv	Four more compressed instructions	2015-07-24 18:24:18 +02:00
controller.sv	Fix ack handling in IF	2015-08-25 15:36:28 +02:00
cs_registers.sv	Move debug from CS registers to debug unit as they do not need to be	2015-08-14 16:31:03 +02:00
debug_unit.sv	Move debug from CS registers to debug unit as they do not need to be	2015-08-14 16:31:03 +02:00
ex_stage.sv	Remove dead signals	2015-08-17 15:19:48 +02:00
exc_controller.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
id_stage.sv	Remove dead signals	2015-08-17 15:19:48 +02:00
if_stage.sv	Fix issue with cross line access and stalls, cleanup	2015-08-25 15:36:28 +02:00
instr_core_interface.sv	Add control FSM to IF stage	2015-08-25 15:34:45 +02:00
load_store_unit.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
mult.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
register_file.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
riscv_core.sv	Fix LUI/AUIPC output of tracer	2015-08-25 15:36:28 +02:00
wb_stage.sv	Remove dead signals	2015-08-17 15:19:48 +02:00