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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
224 commits 21 branches 8 tags 70 MiB
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Sven Stucki b99a8b90ba Raise an illegal instruction exception for ecall/scall instructions. 
Those instructions are no yet supported by the (exception) controller and have
been ignored until now. By causing an exception, they can at least be handled
in software if needed in the future.
2015-11-02 13:35:48 +01:00
docs/datasheet Add a basic datasheet for RI5CY 2015-09-09 18:35:07 +02:00
include Cleanup tracer and defines 2015-10-08 10:47:04 +02:00
.gitignore Added vim swap file 2015-07-24 15:26:32 +02:00
alu.sv Remove some spaces 2015-10-30 13:50:16 +01:00
compressed_decoder.sv Update compressed decoder to RVC 1.9 2015-10-27 12:39:59 +01:00
controller.sv Fix debug breakpoints and single-step with branches in ID 2015-10-29 14:12:50 +01:00
cs_registers.sv Only read CSR when accessed 2015-10-27 14:15:09 +01:00
debug_unit.sv Add test_en to register file clock gates 2015-10-28 12:47:33 +01:00
decoder.sv Raise an illegal instruction exception for ecall/scall instructions. 2015-11-02 13:35:48 +01:00
ex_stage.sv Merge branch 'remove_vect' 2015-10-18 19:57:42 +02:00
exc_controller.sv Fix bug with hardware loops 2015-10-25 19:26:46 +01:00
hwloop_controller.sv Prefix all modules with riscv_ to avoid future conflicts 2015-10-06 12:18:41 +02:00
hwloop_regs.sv Prefix all modules with riscv_ to avoid future conflicts 2015-10-06 12:18:41 +02:00
id_stage.sv Add test_en to core and propagate it to manual clock gates 2015-10-28 10:11:16 +01:00
if_stage.sv Fix debug breakpoints (dbg_set_npc) 2015-10-29 14:01:53 +01:00
load_store_unit.sv Fix typo in last commit 2015-10-16 14:34:33 +02:00
mult.sv Merge branch 'remove_vect' 2015-10-18 19:57:42 +02:00
prefetch_buffer.sv Prefix all modules with riscv_ to avoid future conflicts 2015-10-06 12:18:41 +02:00
prefetch_L0_buffer.sv Prefix all modules with riscv_ to avoid future conflicts 2015-10-06 12:18:41 +02:00
register_file.sv Add test_en to register file clock gates 2015-10-28 12:47:33 +01:00
riscv_core.sv Fix debug breakpoints (dbg_set_npc) 2015-10-29 14:01:53 +01:00