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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
ec00ad8376
Hardware loops now have their own adder and no longer share it with the jump target calculation. The new lp.setupi instruction makes it possible to truly setup hardware loops with a single instruction. For the lp.setup instruction, a register with the counter had to be prepared first. The range of the new instruction is quite limited though, it uses the shifted z-imm (5 bit, unsigned). |
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| docs/datasheet | ||
| include | ||
| .gitignore | ||
| alu.sv | ||
| compressed_decoder.sv | ||
| controller.sv | ||
| cs_registers.sv | ||
| debug_unit.sv | ||
| decoder.sv | ||
| ex_stage.sv | ||
| exc_controller.sv | ||
| hwloop_controller.sv | ||
| hwloop_regs.sv | ||
| id_stage.sv | ||
| if_stage.sv | ||
| load_store_unit.sv | ||
| mult.sv | ||
| prefetch_buffer.sv | ||
| prefetch_L0_buffer.sv | ||
| register_file.sv | ||
| riscv_core.sv | ||