stnolting
31e312ee0c
[ug] remove redundant section
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"Enabling RISC-V CPU Extensions"
2024-01-27 13:28:54 +01:00
Olof Kraigher
7a1536f612
Add VHDL development environment chapter
2023-02-13 21:13:49 +01:00
stnolting
63985a90ff
add new user guide section: NEORV32 in Verilog
2022-08-28 11:43:43 +02:00
stnolting
b6ef834470
[ug] add quick links
2022-07-19 13:34:18 +02:00
stnolting
c04fbf5819
[ug] add new section "LiteX Support"
2022-07-19 12:59:53 +02:00
stnolting
3cb3886205
update documentation
2022-03-31 18:57:17 +02:00
stnolting
7828d0be5d
[docs/userguide] content: added neorv32-setups link
2022-01-19 19:55:09 +01:00
stnolting
ede9f2b44f
[docs/userguide] split user guide into several files
2021-11-29 11:09:33 +01:00
stnolting
82f57d8d39
⚠️ bootloader now stores executable as low-endian to flash
2021-11-28 16:18:04 +01:00
Mario Hoffmann
709d7bfa1c
Added a example serial terminal program for Linux which can easily send files.
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Also fixed a minor typo in the preceding sentence.
2021-11-22 17:37:54 +01:00
stnolting
d3b716dafb
[docs] minor edits regarding DEFAULT mem sources
2021-11-04 00:48:48 +01:00
stnolting
c2f8bab4f7
[docs] typo fixes
2021-10-21 07:35:43 +02:00
stnolting
4e3d495219
[docs/userguide] minor typo fixes
2021-10-19 17:19:03 +02:00
stnolting
fdaaba3a0d
🪁 added link to upstream Zephyr RTOS support
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https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html
port provided by @henrikbrixandersen
2021-10-18 18:36:08 +02:00
stnolting
d2fb1cec8b
[docs/userguide] added note: tri-state driver in vivado block designs
2021-10-18 15:44:02 +02:00
stnolting
d97df66b39
⚠️ modify handling of makefile's MARCH and MABI variables
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Pre-commit usage: `MARCH=-march=rv32i`, the `-march` should not be here
Post-commit usage: `MARCH=rv32i`, this is more straightforward
Same for `MABI=-mabi=...` -> `MABI=...`
2021-10-15 17:20:55 +02:00
stnolting
06d1a7cd28
[docs/userguide] fixed official RISC-V gcc github link
2021-10-14 16:35:29 +02:00
stnolting
a31a24e940
[docs] fixing #181 (em dash vs. en dash)
2021-10-13 11:31:24 +02:00
stnolting
60415610c0
[docs/userguide] added how do breakpoints work
2021-09-28 16:24:37 +02:00
stnolting
96c7462ddc
🐛 [rtl/core] fixed bug in mtime coparator logic
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"time >= timecmp" was not evaluated correctly (the split subword comparator was incorrect), which missed the interrupt for some time/timecmp combinations
2021-09-28 13:17:35 +02:00
stnolting
e3a07321de
[docs/userguide] minot edits
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compilation _with_ debug symbols
2021-09-28 11:56:07 +02:00
stnolting
6cebb7b20a
[docs] minor edits
2021-09-28 08:39:40 +02:00
stnolting
e683d54d3d
[docs/userguide] new section "Adding Custom Hardware Modules"
2021-09-23 17:21:41 +02:00
umarcor
372a3f0a4a
[docs/userguide] update section 'Simulating the Processor'
2021-09-17 16:14:07 +02:00
Rafael Corsi
8e5d985976
[docs/userguide] update simulate instructions (new path)
2021-09-17 16:13:59 +02:00
stnolting
9c9495c69e
[docs] added split IMEM/DMEM
2021-09-13 20:59:03 +02:00
stnolting
0fc4f5cacb
[docs] minor edits
2021-09-11 18:22:33 +02:00
stnolting
c65dcc872e
[docs/ug] reworked simulation section
2021-09-11 08:00:23 +02:00
stnolting
6246f0e8c0
[sw/common] added new makefile target "sim"
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can be used for in-console simulation of current application using GHDL and the default processor testbench ("simple"/script-based testbench setup)
2021-09-10 16:24:06 +02:00
stnolting
5ffee4fc9e
[docs/userguide] minor edits
2021-09-02 19:12:24 +02:00
stnolting
29e11bdec0
[docs/userguide] added new section
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"Application-Specific Processor Configuration"
2021-09-02 17:55:16 +02:00
stnolting
e467decb43
[bootloader] added option to disable SPI module
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and related bootloader options (like load/storing executables from/to SPI flash; SPI auto-boot)
2021-08-19 11:50:21 +02:00
stnolting
9c593549c1
[userguide] added link to new test_setups folder
2021-08-14 09:08:27 +02:00
stnolting
b3797af579
[docs/userguide] added note: (too fast) external clock
2021-08-09 18:06:32 +02:00
stnolting
7c3967f074
[docs/userguide] added signal polarity note
2021-08-09 17:54:20 +02:00
stnolting
c05b9f05c9
[docs/userguide] now using test_setups + minor edits
2021-08-07 16:38:00 +02:00
stnolting
01ec016926
[docs/ug] added Xilinx IP block designer
2021-08-05 16:21:56 +02:00
stnolting
fd51fe7b08
minor edits and updates
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due to moved riscv architecture test folder(s)
2021-07-12 17:07:32 +02:00
stnolting
aa769fa210
Merge branch 'master' of https://github.com/stnolting/neorv32
2021-07-12 16:39:20 +02:00
umarcor
ca8927e558
[sw] use RISCV_PREFIX instead of RISCV_TOOLCHAIN
2021-07-09 23:23:46 +02:00
stnolting
68ebc32590
[docs] added note: priv. arch. extensions in MARCH #112
2021-07-09 17:34:19 +02:00
stnolting
ca719d7876
[docs] updated path to documentation makefile
2021-07-06 21:52:43 +02:00
stnolting
16cfbb63a0
✨ added console options to configure/customize build-in bootloader
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* updated according sections in data sheet and user guide
2021-06-26 20:03:10 +02:00
stnolting
43c418a8b9
[docs] made boot configuration more explicit: DIRECT and INDIRECT
2021-06-16 16:54:48 +02:00
stnolting
4314c3e500
made bootloader more configuration independent
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bootloader only uses the _first_ 512 bytes of the DMEM; hence, DMEM size is irrelevant as long it is >= 512 bytes
2021-06-16 16:28:49 +02:00
stnolting
574b9696a5
🚀 [docs/userguide] reworked and updated entire user guide
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🚧 a few sections are still work-in-progress
2021-06-14 18:50:17 +02:00
stnolting
d4ca543ef1
[docs/userguide] added note to add neorv32 package when instantiating neorv32 top
2021-06-12 22:02:17 +02:00
stnolting
3e128162d3
[docs/datasheet] fixed default testbench name
2021-06-11 17:56:00 +02:00
stnolting
16e27df2b6
[README, docs] updated links to setups folder
2021-06-10 16:44:20 +02:00
stnolting
d086fc66da
[docs] minor link fixes
2021-06-08 16:47:58 +02:00
